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? 2014-2015 microchip technology inc. ds20005262c-page 1 features ? single voltage read and write operations - 2.7-3.6v or 2.3-3.6v ? serial interface architecture - nibble-wide multiplexed i/o?s with spi-like serial command structure - mode 0 and mode 3 - x1/x2/x4 serial peripheral interface (spi) protocol ? high speed clock frequency - 2.7-2.6v: 104 mhz max - 2.3-3.6v: 80 mhz max ? burst modes - continuous linear burst - 8/16/32/64 byte linear burst with wrap-around ? superior reliability - endurance: 100,000 cycles (min) - greater than 100 years data retention ? low power consumption: - active read current: 15 ma (typical @ 104 mhz) - standby current: 15 a (typical) ? fast erase time - sector/block erase: 18 ms (typ), 25 ms (max) - chip erase: 35 ms (typ), 50 ms (max) ? page-program - 256 bytes per page in x1 or x4 mode ? end-of-write detection - software polling the busy bit in status register ? flexible erase capability - uniform 4 kbyte sectors - four 8 kbyte top and bottom parameter overlay blocks - one 32 kbyte top and bottom overlay blocks - uniform 64 kbyte overlay blocks ? write-suspend - suspend program or erase operation to access another block/sector ? software reset (rst) mode ? software write protection - individual-block write protection with permanent lock-down capability - 64 kbyte blocks, two 32 kbyte blocks, and eight 8 kbyte parameter blocks - read protection on top and bottom 8 kbyte parameter blocks ? security id - one-time programmable (otp) 2 kbyte, secure id - 64 bit unique, factory pre-programmed identifier - user-programmable area ? temperature range - industrial: -40c to +85c - extended: -40c to +105c ? packages available - 8-contact wdfn (6mm x 5mm) - 8-lead soij (5.28 mm) - 8-lead soic (3.90 mm) ? all devices are rohs compliant product description the serial quad i/o? (sqi?) family of flash-memory devices features a six-wire, 4-bit i/o interface that allows for low-power, high-performance operation in a low pin-count package. sst26vf016b also supports full command-set compatibility to traditional serial peripheral interface (spi ) protocol. system designs using sqi flash devices occupy less board space and ultimately lower system costs. all members of the 26 series , sqi family are manufac- tured with proprietary, hi gh-performance cmos super- flash? technology. the split-gate cell design and thick- oxide tunneling injector attain better reliability and man- ufacturability compared wit h alternate approaches. sst26vf016b significantly improves performance and reliability, while lowering power consumption. these devices write (program or erase) with a single power supply of 2.3-3.6v. the to tal energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy con- sumed during any erase or program operation is less than alternative flash memory technologies. sst26vf016b is offered in 8-contact wdfn (6 mm x 5 mm), 8-lead soij (5.2 8 mm), and 8-lead soic (3.90 mm). see figures 2-1 through 2-3 for pin assign- ments. sst26vf016b 2.5v/3.0v 16 mbit serial quad i/o (sqi) flash memory
sst26vf016b ds20005262c-page 2 ? 2014-2015 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments rega rding this publication, please contact the marketing communications department via e- mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining it s literature number found on the bottom outside corner of any page. the last character of the literature number is the version number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operati onal differences from the data sheet and re commended workarounds, may exist for curren t devices. as device/documentation i ssues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a partic ular device, pleas e check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2014-2015 microchip technology inc. ds20005262c-page 3 sst26vf016b 1.0 block diagram figure 1-1: functional block diagram 20005262 b1.0 page buffer, i/o buffers and data latches superflash memory x - decoder control logic address buffers and latches hold# y - decoder ce# sio [3:0] serial interface otp wp# sck
sst26vf016b ds20005262c-page 4 ? 2014-2015 microchip technology inc. 2.0 pin description figure 2-1: pin description for 8-lead soij figure 2-2: pin description for 8-contact wdfn figure 2-3: pin description for 8- lead soic 1 2 3 4 8 7 6 5 ce# so/sio1 wp#/sio2 v ss v dd hold/sio3 sck si/sio0 top view 20005262 08-soij s2a p1.0 1 2 3 4 8 7 6 5 ce# so/sio1 wp#/sio2 v ss top view v dd hold/sio3 sck si/sio0 20005262 08-wson qa p1.0 ce# so/sio1 wp#/sio2 v ss v dd hold/sio3 sck si/sio0 20005262 08-soic sa p1.0 1 2 3 4 8 7 6 5 top view table 2-1: pin description symbol pin name functions sck serial clock to provide the timing of the serial interface. commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. sio[3:0] serial data input/output to transfer commands, addresses, or data serially into the device or data out of the device. inputs are latched on the rising edge of the serial clock. data is shifted out on the falling edge of the se rial clock. the enab le quad i/o (eqio) command instruction configures these pins for quad i/o mode. si serial data input for spi mode to transfer commands, addresses or data serially into the device. inputs are latched on the rising edge of the serial clock. si is the default state after a power on reset. so serial data output for spi mode to transfer data serially out of the devi ce. data is shifted out on the falling edge of the serial clock. so is the default state after a power on reset. ce# chip enable the device is enabled by a high to low transition on ce#. ce# must remain low for the duration of any command sequence; or in the case of write operations, for the command/data input sequence. wp# write protect the wp# is used in conjunction with the wpen and ioc bits in the configura- tion register to prohibit write operations to the block-protection register. this pin only works in spi, single-bit and dual-bit read mode. hold# hold temporarily stops serial communication with the spi flash memory while the device is selected. this pin only works in spi, single-bit and dual-bit read mode and must be tied high when not in use. v dd power supply to provide power supply voltage. v ss ground
? 2014-2015 microchip technology inc. ds20005262c-page 5 sst26vf016b 3.0 memory organization the sst26vf016b sqi memory array is organized in uniform, 4 kbyte erasable sectors with the following erasable blocks: eight 8 kbyte parameter, two 32 kbyte overlay, and thirty 64 kbyte overlay blocks. see figure 3-1 . figure 3-1: memory map 20005262 f41.0 top of memory block 8 kbyte 8 kbyte 8 kbyte 8 kbyte 32 kbyte 64 kbyte 64 kbyte 64 kbyte 32 kbyte 8 kbyte 8 kbyte 8 kbyte 8 kbyte bottom of memory block 4 kbyte 4 kbyte 4 kbyte 4 kbyte . . . 2 sectors for 8 kbyte blocks 8 sectors for 32 kbyte blocks 16 sectors for 64 kbyte blocks . . .
sst26vf016b ds20005262c-page 6 ? 2014-2015 microchip technology inc. 4.0 device operation sst26vf016b supports both serial peripheral inter- face (spi) bus protocol and a 4-bit multiplexed sqi bus protocol. to provide backwar d compatibility to tradi- tional spi serial flash device s, the device?s initial state after a power-on reset is spi mode which supports multi-i/o (x1/x2/x4) read/write commands. a com- mand instruction configures the device to sqi mode. the dataflow in the sqi mode is similar to the spi mode, except it uses four multiplexed i/o signals for command, address, and data sequence. sqi flash memory supports both mode 0 (0,0) and mode 3 (1,1) bus operations. the difference between the two modes is the state of the sck signal when the bus master is in stand-by mode and no data is being transferred. the sck signal is low for mode 0 and sck signal is high for mode 3. for both modes, the serial data i/o (sio[3:0]) is samp led at the rising edge of the sck clock signal for input, and driven after the falling edge of the sck clock signal for output. the traditional spi protocol uses separate input (si) and output (so) data signals as shown in figure 4-1 . the sqi protocol uses four multiplexed signals, sio[3:0], for both data in and data out, as shown in figure 4-2 . this means the sqi protocol quadruples th e traditional bus transfer speed at the same clock frequency, without the need for more pins on the package. figure 4-1: spi protocol (tradi tional 25 series spi device) figure 4-2: sqi serial quad i/o protocol 4.1 device protection sst26vf016b offers a flexible memory protection scheme that allows the protection state of each individ- ual block to be controlled separately. in addition, the write-protection lock-down register prevents any change of the lock status during device operation. to avoid inadvertent writes during power-up, the device is write-protected by default after a power-on reset cycle. a global block-protection unlock command offers a single command cycle that unlocks the entire memory array for faster manufacturing throughput. for extra protection, there is an additional non-volatile register that can permanently write-protect the block- protection register bits for each individual block. each of the corresponding lock-down bits are one time pro- grammable (otp)?once wr itten, they cannot be erased. data that had be en previously programmed into these blocks cannot be altered by programming or erase and is not reversible 4.1.1 individual block protection sst26vf016b has a block-protection register which provides a software mechanism to write-lock the indi- vidual memory blocks and write-lock, and/ or read-lock, the individual parameter bl ocks. the block-protection register is 48 bits wide: two bits each for the eight 8 kbyte parameter blocks (wri te-lock and read-lock), and one bit each for the remaining 32 kbyte and 64 kbyte overlay blocks (write-lock). see table 5-6 for address range protected per register bit. each bit in the block-protection register (bpr) can be written to a ?1? (protected) or ?0? (unprotected). for the parameter blocks, the most significant bit is for read- lock, and the least significant bit is for write-lock. read- locking the parameter blocks provides additional secu- rity for sensitive data after re trieval (e.g., after initial boot). if a block is read-locked all reads to the block return data 00h. 20005262 f03.0 mode 3 sck si so ce# mode 3 don't care bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode 0 mode 0 high impedance msb msb 20005262 f04.0 mode 3 clk sio(3:0) ce# mode 3 c1 c0 a5 a4 a3 a2 a1 a0 h0 l0 h1 l1 h2 l2 h3 l3 mode 0 mode 0 msb
? 2014-2015 microchip technology inc. ds20005262c-page 7 sst26vf016b the write block-protection register command is a two-cycle command which requires that write-enable (wren) is executed prior to the write block-protection register command. the global block-protection unlock command clears all write protection bits in the block-protection register. 4.1.2 write-prote ction lock-down (volatile) to prevent changes to the block-protection register, use the lock-down block-protection register (lbpr) command to enable write-protection lock-down. once write-protection lock-down is enabled, the block-protection register ca n not be changed. to avoid inadvertent lock down, the wren command must be executed prior to the lbpr command. to reset write-protection lock-down, performing a power cycle on the device is required. the write-protection lock- down status may be read from the status register. 4.1.3 write-lock lock-down (non- volatile) the non-volatile write-lock lock-down register is an alternate register that permanently prevents changes to the block-protect bits. the non-volatile write-lock lock-down register (nvwldr) is 40 bits wide per device: one bit each for the eight 8-kbyte parameter blocks, and one bit each for the remaining 32 kbyte and 64 kbyte overlay blocks. see table 5-6 for address range protected per register bit. writing ?1? to any or all of the nvwldr bits disables the change mechanism for the corresponding write-lock bit in the bpr, and permanently sets this bit to a ?1? (protected) state. after this change, both bits will be set to ?1?, regardless of the data entered in subsequent writes to either the nv wldr or the bpr. subsequent writes to the nvwldr can only alter available locations that have not been previous ly written to a ?1?. this method provides write-protec tion for the corresponding memory-array block by protecting it from future pro- gram or erase operations. writing a ?0? in any location in the nvwldr has no effect on either the nvwldr or the corresponding write-lock bit in the bpr. note that if the block-prot ection register had been pre- viously locked down, see ?w rite-protection lock-down (volatile)?, the device must be power cycled before using the nvwldr. if the block-protection register is locked down and the write nvwldr command is accessed, the command will be ignored. 4.2 hardware write protection the hardware write protection pin (wp#) is used in con- junction with the wpen and ioc bits in the configuration register to prohibit write operations to the block-protec- tion and configuration registers. the wp# pin function only works in spi single-bit and dual-bit read mode when the ioc bit in the configuration register is set to ?0?. the wp# pin function is disabled when the wpen bit in the configuration register is ?0?. this allows installa- tion of sst26vf016b in a system with a grounded wp# pin while still enabling write to the block-protec- tion register. the lock-down function of the block-pro- tection register supersedes the wp# pin, see table 4- 1 for write protection lock-down states. the factory default setting at power-up of the wpen bit is ?0?, disabling the write protect function of the wp# after power-up. wpen is a non-volatile bit; once the bit is set to ?1?, the write protect function of the wp# pin continues to be enabled after power-up. the wp# pin only protects the block-prot ection register and config- uration register from changes. therefore, if the wp# pin is set to low before or after a program or erase command, or while an internal write is in progress, it will have no effect on the write command. the ioc bit takes priority over the wpen bit in the con- figuration register. when the ioc bit is ?1?, the function of the wp# pin is disabled and the wpen bit serves no function. when the ioc bit is ?0? and wpen is ?1?, set- ting the wp# pin active low prohibits write operations to the block protection register. table 4-1: write protection lock-down states wp# ioc wpen wpld execute wbpr instruction configuration register l0 1 1 not allowed protected l0 0 1 not allowed writable l0 1 0 not allowed protected l0 1 1. default at power-up register settings 0 2 2. factory default setting is ?0?. this is a non-volatile bi t; default at power-up is the value set prior to power-down. 0 allowed writable h0 x 1 not allowed writable h0 x 0 allowed writable x1 x 1 not allowed writable x1 0 2 0 allowed writable
sst26vf016b ds20005262c-page 8 ? 2014-2015 microchip technology inc. 4.3 security id sst26vf016b offers a 2 kbyte security id (sec id) feature. the security id space is divided into two parts ? one factory-programmed, 64-bit segment and one user-programmable segment. the factory-pro- grammed segment is programmed during part manu- facture with a unique number and cannot be changed. the user-programmable segment is left unpro- grammed for the customer to program as desired. use the program security id (psid) command to pro- gram the security id using the address shown in table 5-5 . the security id can be locked using the lockout security id (lsid) command. this prevents any future write operations to the security id. the factory-programmed portion of the security id can?t be programmed by the user; neither the factory- programmed nor user-programmable areas can be erased. 4.4 hold operation the hold# pin pauses active serial sequences with- out resetting the clocking sequence. this pin is active after every power up and only operates during spi single-bit and dual-bit modes . sst26vf016b ships with the ioc bit set to ?0? and the hold# pin function enabled. the hold# pin is always disabled in sqi mode and only works in spi single-bit and dual-bit read mode. to activate the hold mode, ce# must be in active low state. the hold mode begins when the sck active low state coincides with the falling edge of the hold# sig- nal. the hold mode ends when the hold# signal?s ris- ing edge coincides with the sck active low state. if the falling edge of the hold# signal does not coin- cide with the sck active low state, then the device enters hold mode when the sck next reaches the active low state. similarly, if the rising edge of the hold# signal does not coincide with the sck active low state, then the device exits hold mode when the sck next reaches the active low state. see figure 4-3 . once the device enters hold mode, so will be in high impedance state while si and sck can be v il or v ih . if ce# is driven active high during a hold condition, it resets the internal logic of the device. as long as hold# signal is low, the memory remains in the hold condition. to resume communication with the device, hold# must be driven active high, and ce# must be driven active low. figure 4-3: hold co ndition waveform. active hold active hold active 20005262 f46.0 sck hold#
? 2014-2015 microchip technology inc. ds20005262c-page 9 sst26vf016b 4.5 status register the status register is a read-only register that provides the following status information: whether the flash memory array is available for any read or write oper- ation, if the device is wr ite-enabled, whether an erase or program operation is suspended, and if the block- protection register and/or security id are locked down. during an internal erase or program operation, the sta- tus register may be read to determine the completion of an operation in progress. table 4-2 describes the func- tion of each bit in the status register. table 4-2: status register bit name function default at power-up read/write (r/w) 0 busy write operation status 1 = internal write operation is in progress 0 = no internal write operation is in progress 0r 1 wel write-enable latch status 1 = device is write-enabled 0 = device is not write-enabled 0r 2 wse write suspend-erase status 1 = erase suspended 0 = erase is not suspended 0r 3 wsp write suspend-program status 1 = program suspended 0 = program is not suspended 0r 4 wpld write protection lock-down status 1 = write protection lock-down enabled 0 = write protection lock-down disabled 0r 5 sec 1 1. the security id status will always be ?1? at power-up after a successful execution of the lockout security id instruction, ot h- erwise default at power-up is ?0?. security id status 1 = security id space locked 0 = security id space not locked 0 1 r 6 res reserved for future use 0r 7 busy write operation status 1 = internal write operation is in progress 0 = no internal write operation is in progress 0r
sst26vf016b ds20005262c-page 10 ? 2014-2015 microchip technology inc. 4.5.1 write-enable latch (wel) the write-enable latch (wel) bit indicates the status of the internal memory?s write-enable latch. if the wel bit is set to ?1?, the dev ice is write enabled. if the bit is set to ?0? (reset), the device is not write enabled and does not accept any memory program or erase, protection register write, or lock-down commands. the write-enable latch bit is automatically reset under the following conditions: ? power-up ? reset ? write-disable (wrdi) instruction ? page-program instruction completion ? sector-erase instruction completion ? block-erase instruction completion ? chip-erase instruction completion ? write-block-protection register instruction ? lock-down block-protection register instruction ? program security id instruction completion ? lockout security id instruction completion ? write-suspend instruction ? spi quad page program instruction completion ? write status register 4.5.2 write suspend erase status (wse) the write suspend-erase status (wse) indicates when an erase operation has been suspended. the wse bit is ?1? after the host issues a suspend command during an erase operation. once the suspended erase resumes, the wse bi t is reset to ?0?. 4.5.3 write suspend program status (wsp) the write suspend-program status (wsp) bit indicates when a program operation has been suspended. the wsp is ?1? after the host issues a suspend command during the program operation. once the suspended program resumes, the wsp bit is reset to ?0?. 4.5.4 write protection lock-down status (wpld) the write protection lock-d own status (wpld) bit indicates when the block-protection register is locked- down to prevent changes to the protection settings. the wpld is ?1? after the host issues a lock-down block-protection command. after a power cycle, the wpld bit is reset to ?0?. 4.5.5 security id status (sec) the security id status ( sec) bit indicates when the security id space is locked to prevent a write com- mand. the sec is ?1? after the host issues a lockout sid command. once the host issues a lockout sid command, the sec bit can never be reset to ?0.? 4.5.6 busy the busy bit determines whether there is an internal erase or program operation in progress. if the busy bit is ?1?, the device is busy with an internal erase or program operation. if the bit is ?0?, no erase or program operation is in progress. 4.6 configuration register the configuration register is a read/write register that stores a variety of configuration information. see ta b l e 4-3 for the function of ea ch bit in the register. table 4-3: configuration register bit name function default at power-up read/write (r/w) 0 res reserved 0r 1 ioc i/o configuration for spi mode 1 = wp# and hold# pins disabled 0 = wp# and hold# pins enabled 0 1 1. default at power-up is ?0? r/w 2 res reserved 0r 3 bpnv block-protection volatility state 1 = no memory block has been permanently locked 0 = any block has been permanently locked 1r 4 res reserved 0r 5 res reserved 0r 6 res reserved 0r 7 wpen write-protection pin (wp#) enable 1 = wp# enabled 0 = wp# disabled 0 2 2. factory default setting. this is a non-volatile bit; defaul t at power-up will be the setting prior to power-down. r/w
? 2014-2015 microchip technology inc. ds20005262c-page 11 sst26vf016b 4.6.1 i/o configuration (ioc) the i/o configuration (ioc) bit re-configures the i/o pins. the ioc bit is set by writing a ?1? to bit 1 of the configuration register. when ioc bit is ?0? the wp# pin and hold# pin are enabled (spi or dual configuration setup). when ioc bit is set to ?1? the sio2 pin and sio3 pin are enabled (spi quad i/o configuration setup). the ioc bit must be set to ?1? before issuing the follow- ing spi commands: sqor (6bh), sqior (ebh), rbspi (ech), and spi quad page program (32h). without setting the ioc bit to ?1?, those spi commands are not valid. the i/o configuration bit does not apply when in sqi mode. the default at power-up is ?0?. 4.6.2 block-protection volatility state (bpnv) the block-protection volatility state bit indicates whether any block has been permanently locked with the non-volatile write-lock lock-down register (nvwldr). when no bits in the nvwldr have been set, the bpnv is ?1?; this is the default state from the factory. when one or more bits in the nvwldr are set to ?1?, the bpnv bit will be ?0? from that point forward, even after power-up. 4.6.3 write-prote ct enable (wpen) the write-protect enable (wpen) bit is a non-volatile bit that enables the wp# pin. the write-protect (wp#) pi n and the write-protect enable (wpen) bit control the programmable hard- ware write-protect feature. setting the wp# pin to low, and the wpen bit to ?1?, enables hardware write-pro- tection. to disable hardware write protection, set either the wp# pin to high or the wpen bit to ?0?. there is latency associated with writing to the wpen bit. poll the busy bit in the status register, or wait t wpen , for the completion of the inter nal, self-timed write opera- tion. when the chip is har dware write protected, only write operations to block-protection and configuration registers are disabled. see ?hardware write protec- tion? on page 7 and table 4-1 on page 7 for more infor- mation about the functionality of the wpen bit.
sst26vf016b ds20005262c-page 12 ? 2014-2015 microchip technology inc. 5.0 instructions instructions are used to read, write (erase and pro- gram), and configure the sst26vf016b. the com- plete list of the instructions is provided in table 5-1 . table 5-1: device operation instructions for sst26vf016b instruction description command cycle 1 mode address cycle(s) 2, 3 dummy cycle(s) 3 data cycle(s) 3 max 4 freq spi sqi configuration nop no operation 00h x x 0 0 0 104 mhz / 80 mhz rsten reset enable 66h x x 0 0 0 rst 5 reset memory 99h x x 0 0 0 eqio enable quad i/o 38h x 0 0 0 rstqio 6 reset quad i/o ffh x x 0 0 0 rdsr read status register 05h x 0 0 1 to ? x0 11 to ? wrsr write status register 01h x x 0 0 2 rdcr read configuration register 35h x 0 0 1 to ? x0 11 to ? read read read memory 03h x 3 0 1 to ? 40 mhz high- speed read read memory at higher speed 0bh x 3 3 1 to ? 104 mhz / 80 mhz x311 t o ? sqor 7 spi quad output read 6bh x 3 1 1 to ? sqior 8 spi quad i/o read ebh x 3 3 1 to ? sdor 9 spi dual output read 3bh x 3 1 1 to ? sdior 10 spi dual i/o read bbh x 3 1 1 to ? sb set burst length c0h x x 0 0 1 rbsqi sqi read burst with wrap 0ch x 3 3 n to ? rbspi 8 spi read burst with wrap ech x 3 3 n to ? identification jedec-id jedec-id read 9fh x 0 0 3 to ? 104 mhz / 80 mhz quad j-id quad i/o j-id read afh x 0 1 3 to ? sfdp serial flash discoverable parameters 5ah x 3 1 1 to ? write wren write enable 06h x x 0 0 0 104 mhz / 80 mhz wrdi write disable 04h x x 0 0 0 se 11 erase 4 kbytes of memory array 20h x x 3 0 0 be 12 erase 64, 32 or 8 kbytes of memory array d8h x x 3 0 0 ce erase full array c7h x x 0 0 0 pp page program 02h x x 3 0 1 to 256 spi quad pp 7 sqi quad page program 32h x 3 0 1 to 256
? 2014-2015 microchip technology inc. ds20005262c-page 13 sst26vf016b wrsu suspends program/erase b0h x x 0 0 0 104 mhz / 80 mhz wrre resumes program/erase 30h x x 0 0 0 protection rbpr read block-protection register 72h x 0 0 1 to ? 6 104 mhz / 80 mhz x0 11 to ? 6 wbpr write block-protection register 42h x x 0 0 1 to 6 lbpr lock down block-protection register 8dh x x 0 0 0 nvwldr non-volatile write lock- down register e8h x x 0 0 1 to 6 ulbpr global block protection unlock 98h x x 0 0 0 rsid read security id 88h x 2 1 1 to 2048 x 2 3 1 to 2048 psid program user security id area a5h x x 2 0 1 to 256 lsid lockout security id pro- gramming 85h x x 0 0 0 power saving dpd deep power-down mode b9h x x 0 0 0 104 mhz / 80 mhz rdpd release from deep power- down and read id abh x x 3 0 1 to ? 1. command cycle is two clock periods in sq i mode and eight clock periods in spi mode. 2. address bits above the most signi ficant bit of each density can be v il or v ih. 3. address, dummy/mode bits, and data cycles are two cloc k periods in sqi and eight clock periods in spi mode. 4. the max frequency for all instructions is up to 104 mhz from 2.7-3.6v and up to 80 mhz from 2.3-3.6v unless otherwise noted. 5. rst command only executed if rste n command is executed first. any inte rvening command will disable reset. 6. device accepts eight-clock command in spi mode, or two-clock command in sqi mode. 7. data cycles are two clock periods. ioc bit must be set to ?1? before issuing the command. 8. address, dummy/mode bits, and data cycles are two clock periods. ioc bit must be set to ?1? before issuing the command. 9. data cycles are four clock periods. 10. address, dummy/mode bits, and data cycles are four clock periods. 11. sector addresses: use a ms - a 12 , remaining address are don?t care, but must be set to v il or v ih . 12. blocks are 64 kbyte, 32 kbyte, or 8kbyte, depend ing on location. block erase address: a ms - a 16 for 64 kbyte; a ms - a 15 for 32 kbyte; a ms - a 13 for 8 kbyte. remaining addresses are don?t care, but must be set to v il or v ih . table 5-1: device operation instructions for sst26vf016b instruction description command cycle 1 mode address cycle(s) 2, 3 dummy cycle(s) 3 data cycle(s) 3 max 4 freq spi sqi
sst26vf016b ds20005262c-page 14 ? 2014-2015 microchip technology inc. 5.1 no operation (nop) the no operation command only cancels a reset enable command. nop has no impact on any other command. 5.2 reset-enable (rsten) and reset (rst) the reset operation is used as a system (software) reset that puts the device in normal operating ready mode. this operation consists of two commands: reset-enable (rsten) followed by reset (rst). to reset sst26vf016b, the host drives ce# low, sends the reset-enable command (66h), and drives ce# high. next, the host drives ce# low again, sends the reset command (99h), and drives ce# high, see figure 5-1 . the reset operation requires the reset-enable com- mand followed by the reset command. any command other than the reset command after the reset-enable command will disable the reset-enable. once the reset-enable and reset commands are suc- cessfully executed, the devic e returns to normal opera- tion read mode and then does the following: resets the protocol to spi mode, resets the burst length to 8 bytes, clears all the bits, except for bit 4 (wpld) and bit 5 (sec), in the status regi ster to their default states, and clears bit 1 (ioc) in the c onfiguration register to its default state. a device reset during an active program or erase operation aborts the operation, which can cause the data of the targeted address range to be cor- rupted or lost. depending on the prior operation, the reset timing may vary. recovery from a write operation requires more latency time than recovery from other operations. see table 8-2 on page 46 for rest timing parameters. figure 5-1: reset sequence 5.3 read (40 mhz) the read instruction, 03h, is supported in spi bus pro- tocol only with clock frequencies up to 40 mhz. this command is not supported in sqi bus protocol. the device outputs the data st arting from the specified address location, then continuously streams the data output through all addresses until terminated by a low- to-high transition on ce#. the internal address pointer will automatically incremen t until the highest memory address is reached. once the highest memory address is reached, the address pointer will automatically return to the beginning (wrap-around) of the address space. initiate the read instruction by executing an 8-bit com- mand, 03h, followed by address bits a[23:0]. ce# must remain active low for the duration of the read cycle. see figure 5-2 for read sequence. figure 5-2: read sequence (spi) 2005262 f05.0 mode 3 clk sio(3:0) ce# mode 3 c1 c3 c2 c0 mode 0 mode 3 mode 0 mode 0 t cph note: c[1:0] = 66h; c[3:2] = 99h 20005262 f29.0 ce# so si sck add. 01234567 8 add. add. 03 high impedance 15 16 23 24 31 32 39 40 70 47 4 8 55 56 63 64 n+2 n+3 n+4 n n+1 d out msb msb msb mode 0 mode 3 d out d out d out d out
? 2014-2015 microchip technology inc. ds20005262c-page 15 sst26vf016b 5.4 enable quad i/o (eqio) the enable quad i/o (eqio) instruction, 38h, enables the flash device for sqi bus operation. upon comple- tion of the instruction, all instructions thereafter are expected to be 4-bit multiplexed input/output (sqi mode) until a power cycle or a ?reset quad i/o instruc- tion? is executed. see figure 5-3 . figure 5-3: enable quad i/o sequence 5.5 reset quad i/o (rstqio) the reset quad i/o instruction, ffh, resets the device to 1-bit spi protocol operation or exits the set mode configuration during a read sequence. this command allows the flash device to return to the default i/o state (spi) without a power cycle, an d executes in either 1- bit or 4-bit mode. if the device is in the set mode con- figuration, while in sqi high-speed read mode, the rstqio command will only return the device to a state where it can accept new command instruction. an addi- tional rstqio is required to reset the device to spi mode. to execute a reset quad i/o operation, the host drives ce# low, sends the rese t quad i/o command cycle (ffh) then, drives ce# high . execute the instruction in either spi (8 clocks) or sqi (2 clocks) command cycles. for spi, sio[3:1] are don?t care for this com- mand, but should be driven to v ih or v il . see figures 5-4 and 5-5 . figure 5-4: reset quad i/o sequence (spi) figure 5-5: reset quad i/o sequence (sqi) 20005262 f43.0 mode 3 0 1 sck sio0 ce# mode 0 234567 38 sio[3:1] note: sio[3:1] must be driven v ih 20005262 f73.0 mode 3 0 1 sck sio0 ce# mode 0 234567 ff sio[3:1] note: sio[3:1] must be driven v ih 20005262 f74.0 mode 3 0 1 sck sio(3:0) ce# f f mode 0
sst26vf016b ds20005262c-page 16 ? 2014-2015 microchip technology inc. 5.6 high-speed read the high-speed read instruct ion, 0bh, is supported in both spi bus protocol and sqi protocol. this instruc- tion supports frequencies of up to 104 mhz from 2.7- 3.6v and up to 80 mhz from 2.3-3.6v. on power-up, the device is set to use spi. initiate high-speed read by executing an 8-bit com- mand, 0bh, followed by address bits a[23-0] and a dummy byte. ce# must remain active low for the dura- tion of the high-speed read cycle. see figure 5-6 for the high-speed read sequenc e for spi bus protocol. figure 5-6: high-speed read sequence (spi) (c[1:0] = 0bh) in sqi protocol, the host dr ives ce# low then sends one high-speed r ead command cycle, 0bh, followed by three address cycles, a set mode configuration cycle, and two dummy cycles. each cycle is two nibbles (clocks) long, most significant nibble first. after the dummy cycles, the device outputs data on the falling edge of the sck signal starting from the speci- fied address location. the device continually streams data output through all addresses until terminated by a low-to-high transition on ce#. the internal address pointer automatically increm ents until the highest mem- ory address is reached, at which point the address pointer returns to address location 000000h. during this operation, blocks that are read-lock ed will output data 00h. the set mode configuration bit m[7:0] indicates if the next instruction cycle is another sqi high-speed read command. when m[7:0] = axh , the device expects the next continuous instruction to be another read com- mand, 0bh, and does not require the op-code to be entered again. the host may initiate the next read cycle by driving ce# low, then sending the four-bits input for address a[23:0], followed by the set mode configuration bits m[7:0], and two dummy cycles. after the two dummy cycles, the device outputs the data starting from the specified address location. there are no restrictions on ad dress location access. when m[7:0] is any value other than axh, the device expects the next instruction initiated to be a command instruction. to reset/exit the set mode configuration, execute the reset quad i/o command, ffh. while in the set mode configuration, the rstqio command will only return the device to a state where it can accept new command instruction. an additional rstqio is required to reset the device to spi mode. see figure 5- 10 for the spi quad i/o mode read sequence when m[7:0] = axh. figure 5-7: high-speed read sequence (sqi) 20005262 f31.0 ce# so/sio1 si/sio0 sck add. 01234567 8 add. add. 0b high impedance 15 16 23 24 31 32 39 40 47 4 8 55 56 63 64 n+2 n+3 n+4 n n+1 x msb mode 0 mode 3 d out d out d out d out 80 71 72 d out address du mmy command command data byte 0 msn lsn data byte 7 mode 20005262 f47.0 012 sck sio(3:0) ce# c1c0 a5 a4 a3 a2 a1 a0 xh0 xxx l0 h 8 l 8 7 8 1110 91 3 12 1514 2120 mode 3 mode 0 3456 m1 m0 note: msn= most significant nibble, lsn = least significant nibble hx = high data nibble, lx = low data nibble c[1:0]=0bh
? 2014-2015 microchip technology inc. ds20005262c-page 17 sst26vf016b 5.7 spi quad-output read the spi quad-output read instruction supports fre- quencies of up to 104 mhz from 2.7-3.6v and up to 80 mhz from 2.3-3.6v. sst26vf016b requires the ioc bit in the configuration register to be set to ?1? prior to exe- cuting the command. initiate spi quad-output read by executing an 8-bit command, 6bh, followed by address bits a[23-0] and a dummy byte. ce# must remain active low for the duration of the spi quad mode read. see figure 5-8 for the spi quad output read sequence. following the dummy byte, the device outputs data from sio[3:0] starting from the specified address loca- tion. the device continually streams data output through all addresses until terminated by a low-to-high transition on ce#. the internal address pointer auto- matically increments until the highest memory address is reached, at which point the address pointer returns to the beginning of the address space. figure 5-8: spi quad output read ce# sio0 sck 012345678 31 32 24 mode 3 mode 0 15 16 23 6bh 20005262 f48.3 39 40 41 a[23:16] a[15:8 ] a[7:0] b 4 b 0 b 4 b 0 b 5 b 1 b 5 b 1 b 6 b 2 b 6 b 2 b 7 b 3 b 7 b 3 sio1 sio2 sio3 address op code data byte 0 du mmy data byte n x note: msn= most significant nibble, lsn = least significant nibble
sst26vf016b ds20005262c-page 18 ? 2014-2015 microchip technology inc. 5.8 spi quad i/o read the spi quad i/o read (sqior) instruction supports frequencies of up to 104 mhz from 2.7-3.6v and up to 80 mhz from 2.3-3.6v. sst26vf016b requires the ioc bit in the configuration re gister to be set to ?1? prior to executing the command. initiate sqior by execut- ing an 8-bit command, ebh. the device then switches to 4-bit i/o mode for address bits a[23-0], followed by the set mode configuration bits m[7:0], and two dummy bytes.ce# must remain active low for the duration of the spi quad i/o read. see figure 5-9 for the spi quad i/o read sequence. following the dummy bytes, the device outputs data from the specified address location. the device contin- ually streams data output through all addresses until terminated by a low-to-high transition on ce#. the internal address pointer automatically increments until the highest memory address is reached, at which point the address pointer returns to the beginning of the address space. the set mode configuration bi t m[7:0] indicates if the next instruction cycle is another spi quad i/o read command. when m[7:0] = axh, the device expects the next continuous instruction to be another read com- mand, ebh, and does not require the op-code to be entered again. the host ma y set the next sqior cycle by driving ce# low, then sending the four-bit wide input for address a[23:0], followed by the set mode configu- ration bits m[7:0], and tw o dummy cycles. after the two dummy cycles, the device ou tputs the data starting from the specified address location. there are no restrictions on address location access. when m[7:0] is any value other than axh, the device expects the next instruction initiated to be a command instruction. to reset/exit the set mode configuration, execute the reset quad i/o command, ffh. see fig- ure 5-10 for the spi quad i/o mode read sequence when m[7:0] = axh. figure 5-9: spi quad i/o read sequence a20 a16 a12 a 8 a4 a0 m4 m0 ce# sio0 sck 012345678 16 17 12 mode 3 mode 0 91011 ebh 20005262 f49.2 b 4 b 0 sio1 sio2 sio3 address data byte 0 du mmy 1513 14 23 19 18 2220 21 b 4 b 0 a21 a17 a13 a9 a5 a1 m5 m1 b 5 b 1 b 5 b 1 a22 a18 a14 a10 a6 a2 m6 m2 b 6 b 2 b 6 b 2 a23 a19 a15 a11 a7 a3 m7 m3 b 7 b 3 b 7 b 3 set mode data byte 1 msn lsn x x x x x x x x x x x x x x x x note: msn= most significant nibble, lsn = least significant nibble
? 2014-2015 microchip technology inc. ds20005262c-page 19 sst26vf016b figure 5-10: back-to-back spi quad i /o read sequences when m[7:0] = axh 5.9 set burst the set burst command specifies the number of bytes to be output during a read burst command before the device wraps around. it sup ports both spi and sqi pro- tocols. to set the burst length the host drives ce# low, sends the set burst comma nd cycle (c0h) and one data cycle, then drives ce# high. after power-up or reset, the burst length is set to eight bytes (00h). see table 5-2 for burst length data and figures 5-11 and 5- 12 for the sequences. figure 5-11: set burst length sequence (sqi) a20 a16 a12 a 8 a4 a0 m4 m0 ce# sio0 sck 01 9 10 5 23 4 20005262 f50.2 b 4 b 0 sio1 sio2 sio3 address data byte 0 du mmy 8 67 1211 13 b 4 b 0 set mode msn lsn b 4 b 0 x x x x a21 a17 a13 a9 a5 a1 m5 m1 b 5 b 1 b 5 b 1 b 5 b 1 x x x x a22 a18 a14 a10 a6 a2 m6 m2 b 6 b 2 b 6 b 2 b 6 b 2 x x x x a23 a19 a15 a11 a7 a3 m7 m3 b 7 b 3 b 7 b 3 b 7 b 3 x x x x data byte n data byte n+1 note: msn= most significant nibble, lsn = least significant nibble table 5-2: burst length data burst length high nibble (h0) low nibble (l0) 8 bytes 0h 0h 16 bytes 0h 1h 32 bytes 0h 2h 64 bytes 0h 3h 20005262 f32.0 mode 3 0 1 sck sio(3:0) ce# c1 c0 mode 0 23 h0 l0 msn lsn note: msn = most significant nibble, lsn = least significant nibble, c[1:0]=c0h
sst26vf016b ds20005262c-page 20 ? 2014-2015 microchip technology inc. figure 5-12: set burst length sequence (spi) 5.10 sqi read burst with wrap (rbsqi) sqi read burst with wrap is similar to high speed read in sqi mode, except data will output continuously within the burst le ngth until a low-to-high transition on ce#. to execute a sqi read burst operation, drive ce# low then send the read burst command cycle (0ch), followed by three address cycles, and then three dummy cycles. each cycle is two nibbles (clocks) long, most significant nibble first. after the dummy cycles, the device outputs data on the falling edge of the sck signal starting from the speci- fied address location. the data output stream is contin- uous through all addresses until terminated by a low-to- high transition on ce#. during rbsqi, the inter nal address pointer automati- cally increments until the last byte of the burst is reached, then it wraps around to the first byte of the burst. all bursts are aligned to addresses within the burst length, see table 5-3 . for example, if the burst length is eight bytes, and the start address is 06h, the burst sequence would be: 06h, 07h, 00h, 01h, 02h, 03h, 04h, 05h, 06h, etc. the pattern repeats until the command is terminated by a low-to-high transition on ce#. during this operation, blocks that are read-locked will output data 00h. 5.11 spi read burst with wrap (rbspi) spi read burst with wrap (rbspi) is similar to spi quad i/o read except the data will output continuously within the burst l ength until a low-to-high transition on ce#. to execute a spi read burst with wrap opera- tion, drive ce# low, then send the read burst com- mand cycle (ech), followed by three address cycles, and then three dummy cycles. after the dummy cycle, the device outputs data on the falling edge of the sck signal starting from the speci- fied address location. the data output stream is contin- uous through all addresses until terminated by a low-to- high transition on ce#. during rbspi, the in ternal address pointer automati- cally increments until the last byte of the burst is reached, then it wraps around to the first byte of the burst. all bursts are aligned to addresses within the burst length, see table 5-3 . for example, if the burst length is eight bytes, and the start address is 06h, the burst sequence would be: 06h, 07h, 00h, 01h, 02h, 03h, 04h, 05h, 06h, etc. the pattern repeats until the command is terminated by a low-to-high transition on ce#. during this operation, blocks that are read-locked will output data 00h. ce# sio0 sck 012345678 12 mode 3 mode 0 91011 c0 20005262 f51.0 sio[3:1] 1513 14 d in note: sio[3:1] must be driven v ih . table 5-3: burst address ranges burst length burst address ranges 8 bytes 00-07h, 08-0fh, 10-17h, 18-1fh... 16 bytes 00-0fh, 10-1fh, 20-2fh, 30-3fh... 32 bytes 00-1fh, 20-3fh, 40-5fh, 60-7fh... 64 bytes 00-3fh, 40-7fh, 80-bfh, c0-ffh 0
? 2014-2015 microchip technology inc. ds20005262c-page 21 sst26vf016b 5.12 spi dual-output read the spi dual-output read instruction supports fre- quencies of up to 104 mhz from 2.7-3.6v and up to 80 mhz from 2.3-3.6v. initiate spi dual-output read by executing an 8-bit command, 3bh, followed by address bits a[23-0] and a dummy byte. ce# must remain active low for the duration of the spi dual-output read operation. see figure 5-13 for the spi quad output read sequence. following the dummy byte, sst26vf016b outputs data from sio[1:0] starting from the specified address location. the device cont inually streams data output through all addresses until terminated by a low-to-high transition on ce#. the internal address pointer auto- matically increments until the highest memory address is reached, at which point the address pointer returns to the beginning of the address space. figure 5-13: fast read, dual-output sequence 5.13 spi dual i/o read the spi dual i/o read (sdior) instruction supports up to 80 mhz frequency. initiate sdior by executing an 8-bit command, bbh. the device then switches to 2-bit i/o mode for address bits a[23-0], followed by the set mode configuration bits m[7:0].ce# must remain active low for the duration of the spi dual i/o read. see figure 5-14 for the spi dual i/o read sequence. following the set mode configuration bits, the sst26vf016b outputs data from the specified address location. the device continually streams data output through all addresses until terminated by a low-to-high transition on ce#. the in ternal address pointer auto- matically increments until the highest memory address is reached, at which point the address pointer returns to the beginning of the address space. the set mode configuration bit m[7:0] indicates if the next instruction cycle is ano ther spi dual i/o read command. when m[7:0] = axh , the device expects the next continuous instruction to be another sdior com- mand, bbh, and does not require the op-code to be entered again. the host may set the next sdior cycle by driving ce# low, then sending the two-bit wide input for address a[23:0], followed by the set mode configu- ration bits m[7:0]. after the set mode configuration bits, the device outputs the data starting from the specified address location. there are no restrictions on address location access. when m[7:0] is any value other than axh, the device expects the next instruction initiated to be a command instruction. to reset/exit the set mode configuration, execute the reset quad i/o command, ffh. see fig- ure 5-15 for the spi dual i/o read sequence when m[7:0] = axh. ce# sio0 sck 012345678 31 32 24 mode 3 mode 0 15 16 23 3bh 20005262 f52.3 39 40 41 a[23:16] a[15:8 ] a[7:0] b 6 b 5 b 6 b 5 sio1 address op code data byte 0 du mmy data byte n b 3 b 1 b 3 b 1 b 7 b 4 b 7 b 4 b 2 b 0 b 2 b 0 msb x note: msb = most significant bit.
sst26vf016b ds20005262c-page 22 ? 2014-2015 microchip technology inc. figure 5-14: spi dual i/o read sequence figure 5-15: back-to-back spi dual i/o read sequences when m[7:0] = axh 7 5 3 1 7 5 3 1 7 5 3 1 7 5 6 4 2 0 ce# sio0 sck 012345678 16 17 12 mode 3 mode 0 91011 20005262 f53.1 sio1 a[23:16] 1513 14 23 191 8 2220 21 6 4 2 0 6 4 2 0 6 4 a[15:8] a[7:0] m[7:0] 7 5 3 1 7 5 3 1 7 5 3 1 7 5 4 2 0 ce# (cont?) sio0 (cont?) sck (cont?) 23 24 32 33 28 25 26 27 sio1 (cont?) byte 0 3129 30 39 3534 3 8 36 37 6 4 2 0 6 4 2 0 6 4 byte 1 byte 2 byte 3 2 0 6 3 1 7 msb msb msb 6 msb i/o switches from input to output bbh note: msb= most significant bit, lsb = least significant bit 7 5 3 1 7 5 3 1 7 5 3 1 7 5 mode 3 mode 0 6 4 2 0 ce# sio0 sck 0 8 9 4 12 3 20005262 f54.1 sio1 a[23:16] 7 56 15 1110 1412 13 6 4 2 0 6 4 2 0 6 4 a[15:8] a[7:0] m[7:0] 7 5 3 1 7 5 3 1 7 5 3 1 7 5 4 2 0 ce# (cont?) sio0 (cont?) sck (cont?) 15 16 24 25 20 17 1 8 19 sio1 (cont?) byte 0 2321 22 31 2726 302 8 29 6 4 2 0 6 4 2 0 6 4 byte 1 byte 2 byte 3 2 0 6 3 1 7 msb msb msb 6 msb 7 5 7 5 3 1 4 6 4 2 0 msb 6 msb i/o switches from input to output i/o switch note: msb= most significant bit, lsb = least significant bit
? 2014-2015 microchip technology inc. ds20005262c-page 23 sst26vf016b 5.14 jedec-id read (spi protocol) using traditional spi protocol, the jedec-id read instruction identifies the device as sst26vf016b and the manufacturer as microc hip?. to execute a jecec- id operation the host drives ce# low then sends the jedec-id command cycle (9fh). immediately following the command cycle, sst26vf016b output data on the falling edge of the sck signal. the data output st ream is continuous until terminated by a low-to-high transition on ce#. the device outputs three bytes of data: manufacturer, device type, and device id, see table 5-4 . see figure 5-16 for instruction sequence. figure 5-16: jedec-id sequence (spi) 5.15 read quad j-id read (sqi protocol) the read quad j-id read instruction identifies the device as sst26vf016b and manufacturer as micro- chip. to execute a quad j-id operation the host drives ce# low and then sends the quad j-id command cycle (afh). each cycle is two nibbles (clocks) long, most significant nibble first. immediately following the command cycle and one dummy cycle, sst26vf016b ou tputs data on the fall- ing edge of the sck signal. the data output stream is continuous until terminated by a low-to-high transition of ce#. the device outputs three bytes of data: manu- facturer, device type, and device id, see table 5-4 . see figure 5-17 for instruction sequence. figure 5-17: quad j-id read sequence table 5-4: device id data output product manufacturer id (byte 1) device id device type (byte 2) device id (byte 3) sst26vf016b bfh 26h 41h 26 de vice id 20005262 f38.0 ce# so si sck 012345678 high impedance 15 1614 28 29 30 31 bf mode 3 mode 0 msb msb 9 10111213 171 8 32 34 9f 19 20 21 22 23 33 24 25 26 27 bfh de vice id du mmy bfh msn lsn 26h 26h n 20005262 f55.0 012 sck sio(3:0) ce# c1c0 x x h0 l0 h1 l1 h0 l1h1l0 hn ln 7 8 1110 91 3 12 n mode 3 mode 0 3456 h2 l2 note: ms n = most significant n ibble; lsn = least significant n ibble. c{1:0]=afh
sst26vf016b ds20005262c-page 24 ? 2014-2015 microchip technology inc. 5.16 serial flash discoverable parameters (sfdp) the serial flash discoverable parameters (sfdp) contain information describing the characteristics of the device. this allows device-independent, jedec id- independent, and forward/backward compatible soft- ware support for all future serial flash device families. see table 11-1 on page 58 for address and data val- ues. initiate sfdp by executing an 8-bit command, 5ah, fol- lowed by address bits a[23-0] and a dummy byte. ce# must remain active low for the duration of the sfdp cycle. for the sfdp sequence, see figure 5-18 . figure 5-18: serial flash di scoverable param eters sequence 5.17 sector-erase the sector-erase instructio n clears all bits in the selected 4 kbyte sector to ?1,? but it does not change a protected memory area. pr ior to any write operation, the write-enable (wren) instruction must be exe- cuted. to execute a sector-erase operation, the host drives ce# low, then sends the sector erase command cycle (20h) and three address cycles, and then drives ce# high. address bits [a ms :a 12 ] (a ms = most significant address) determine the sector address (sa x ); the remaining address bits can be v il or v ih . to identify the completion of the internal, self-timed, write operation, poll the busy bit in the status register, or wait t se . see figures 5-19 and 5-20 for the sector-erase sequence. figure 5-19: 4 kbyte sector-erase sequence? sqi mode figure 5-20: 4 kbyte secto r-erase sequence (spi) 20005262 f56.0 ce# so si sck add. 01234567 8 add. add. 5a high impedance 15 16 23 24 31 32 39 40 47 4 8 55 56 63 64 n+2 n+3 n+4 n n+1 x msb mode 0 mode 3 d out d out d out d out 80 71 72 d out 20005262 f07.0 mode 3 0 1 sck sio(3:0) ce# c1 c0 mode 0 2 a5 a4 msn lsn 4 a3 a2 6 a1 a0 note: msn = most significant nibble, lsn = least significant nibble, c[1:0] = 20h ce# so si sck add. 01234567 8 add. add. 20 high impedance 15 16 23 24 31 mode 0 mode 3 20005262 f57.0 msb msb
? 2014-2015 microchip technology inc. ds20005262c-page 25 sst26vf016b 5.18 block-erase the block-erase instruction clears all bits in the selected block to ?1?. bl ock sizes can be 8 kbyte, 32 kbyte or 64 kbyte depending on address, see figure 3-1 , memory map, for details. a block-erase instruction applied to a protected memory area will be ignored. prior to any write operation, execute the wren instruc- tion. keep ce# active low for the duration of any com- mand sequence. to execute a block-erase operation, the host drives ce# low then sends the block-erase command cycle (d8h), three address cycles, then drives ce# high. address bits a ms -a 13 determine the block address (ba x ); the remaining address bits can be v il or v ih . for 32 kbyte blocks, a 14 :a 13 can be v il or v ih ; for 64 kbyte blocks, a 15 :a 13 can be v il or v ih . poll the busy bit in the status register, or wait t be, for the completion of the internal, self-timed, block-erase operation. see figures 5-21 and 5-22 for the block-erase sequence. figure 5-21: block-erase sequence (sqi) figure 5-22: block-erase sequence (spi) 20005262 f08.0 mode 3 0 1 sck sio(3:0) ce# c1 c0 mode 0 2 a5 a4 msn lsn 4 a3 a2 6 a1 a0 note: msn = most significant nibble, lsn = least significant nibble c[1:0] = d8h ce# so si sck addr 01234567 8 addr addr d8 high impedance 15 16 23 24 31 mode 0 mode 3 20005262 f58.0 msb msb
sst26vf016b ds20005262c-page 26 ? 2014-2015 microchip technology inc. 5.19 chip-erase the chip-erase instruction clears all bits in the device to ?1.? the chip-erase instruction is ignored if any of the memory area is protected. prior to any write operation, execute the wren instruction. to execute a chip-erase operation, the host drives ce# low, sends the chip-erase command cycle (c7h), then drives ce# high. poll the busy bit in the status register, or wait t sce, for the completion of the internal, self-timed, write operation. see figures 5-23 and 5-24 for the chip erase sequence. figure 5-23: chip-erase sequence (sqi) figure 5-24: chip-er ase sequence (spi) 20005262 9.1 mode 3 0 1 sck sio(3:0) ce# c1 c0 mode 0 note: c[1:0] = c7h ce# so si sck 01234567 c7 high impedance mode 0 mode 3 20005262 f59.0 msb
? 2014-2015 microchip technology inc. ds20005262c-page 27 sst26vf016b 5.20 page-program the page-program instruction programs up to 256 bytes of data in the memory, and supports both spi and sqi protocols. the data for the selected page address must be in the erased state (ffh) before initi- ating the page-program operation. a page-program applied to a protected memory area will be ignored. prior to the program operation, execute the wren instruction. to execute a page-program operation, the host drives ce# low then sends the page program command cycle (02h), three address cycles followed by the data to be programmed, then drives ce# high. the programmed data must be between 1 to 256 bytes and in whole byte increments; sending less than a full byte will cause the partial byte to be ignored. poll the busy bit in the sta- tus register, or wait t pp, for the completion of the inter- nal, self-timed, write operation. see figures 5-25 and 5-26 for the page-program sequence. when executing page-program, the memory range for the sst26vf016b is divided into 256 byte page boundaries. the device handles shifting of more than 256 bytes of data by maintaining the last 256 bytes of data as the correct data to be programmed. if the target address for the page-program instruction is not the beginning of the page boundary (a[7:0] are not all zero), and the number of bytes of data input exceeds or overlaps the end of the address of the page boundary, the excess data inputs wrap around and will be pro- grammed at the start of that target page. figure 5-25: page-program sequence (sqi) figure 5-26: page-pr ogram sequence (spi) 20005262 f10.1 mode 3 0 sck sio(3:0) ce# c1 c0 mode 0 2 a5 a4 msn lsn 4 a3 a2 6 a1 a0 8 h0 l0 10 h1 l1 12 h2 l2 hn ln data byte 0 data byte 1 data byte 2 data byte 255 note: msn = most significant nibble, lsn = least significant nibble c[1:0] = 02h 20005262 f60.1 ce# so si sck add. 01234567 8 add. add. data byte 0 02 high impedance 15 16 23 24 31 32 39 mode 0 mode 3 msb msb msb lsb ce# (cont?) so (cont?) si (cont?) sck (cont?) 40 41 42 43 44 45 46 47 4 8 data byte 1 high impedance msb msb msb lsb 50 51 52 53 54 55 2072 49 data byte 2 2073 2074 2075 2076 2077 2078 2079 data byte 255 lsb lsb lsb lsb
sst26vf016b ds20005262c-page 28 ? 2014-2015 microchip technology inc. 5.21 spi quad page-program the spi quad page-program instruction programs up to 256 bytes of data in the memory. the data for the selected page address must be in the erased state (ffh) before initiating the spi quad page-program operation. a spi quad page-program applied to a pro- tected memory area will be ignored. sst26vf016b requires the ico bit in the configuration register to be set to ?1? prior to executing the command. prior to the program operation, execut e the wren instruction. to execute a spi quad page-program operation, the host drives ce# low then sends the spi quad page- program command cycle (32h), three address cycles followed by the data to be programmed, then drives ce# high. the programmed data must be between 1 to 256 bytes and in whole byte increments. the com- mand cycle is eight clocks long, the address and data cycles are each two clocks l ong, most sign ificant bit first. poll the busy bit in t he status register, or wait t pp, for the completion of the internal, self-timed, write operation.see figure 5-27 . when executing spi quad page-program, the memory range for the sst26vf016b is divided into 256 byte page boundaries. the device handles shifting of more than 256 bytes of data by maintaining the last 256 bytes of data as the correct data to be programmed. if the target address for the spi quad page-program instruction is not the beginning of the page boundary (a[7:0] are not all zero), and the of bytes of data input exceeds or overlaps the end of the address of the page boundary, the excess data inputs wrap around and will be programmed at the start of that target page. figure 5-27: spi quad page-program sequence 5.22 write-suspend and write-resume write-suspend allows the interruption of sector-erase, block-erase, spi quad p age-program, or page-pro- gram operations in order to erase, program, or read data in another portion of memory. the original opera- tion can be continued with the write-resume com- mand. this operation is supported in both sqi and spi protocols. only one write operation can be suspended at a time; if an operation is already suspended, the device will ignore the write-suspend command. write-suspend during chip-erase is ignored; chip-erase is not a valid command while a write is suspended. the write- resume command is ignored until any write operation (program or erase) initia ted during the write-suspend is complete. the device requires a minimum of 500 s between each write-suspend command. 5.23 write-suspend during sector- erase or block-erase issuing a write-suspend instruction during sector- erase or block-erase allows the host to program or read any sector that was not being erased. the device will ignore any programming commands pointing to the suspended sector(s). any attempt to read from the sus- pended sector(s) will output unknown data because the sector- or block-erase will be incomplete. to execute a write-suspend operation, the host drives ce# low, sends the write suspend command cycle (b0h), then drives ce# high. the status register indi- cates that the erase has been suspended by changing the wse bit from ?0? to ?1,? but the device will not accept another command until it is ready. to determine when the device will accept a new command, poll the busy bit in the status register or wait t ws . a20 a16 a12 a 8 a4 a0 b 4 b 0 ce# sio0 sck 012345678 16 17 12 mode 3 mode 0 91011 32h 20005262 f61.1 sio1 sio2 sio3 address data byte 1 1513 14 a21 a17 a13 a9 a5 a1 b 5 b 1 b 5 b 1 b 5 b 1 a22 a18 a14 a10 a6 a2 b 6 b 2 b 6 b 2 b 6 b 2 a23 a19 a15 a11 a7 a3 b 7 b 3 b 7 b 3 b 7 b 3 data byte 0 data byte 255 msn lsn b 4 b 0 b 4 b 0
? 2014-2015 microchip technology inc. ds20005262c-page 29 sst26vf016b 5.24 write suspend during page programming or spi quad page programming issuing a write-suspend instruction during page pro- gramming allows the host to erase or read any sector that is not being programmed. erase commands point- ing to the suspended sector(s) will be ignored. any attempt to read from the suspended page will output unknown data because the program will be incomplete. to execute a write suspend operation, the host drives ce# low, sends the write suspend command cycle (b0h), then drives ce# high. the status register indi- cates that the programming has been suspended by changing the wsp bit from ?0? to ?1,? but the device will not accept another command until it is ready. to deter- mine when the device will accept a new command, poll the busy bit in the status register or wait t ws . 5.25 write-resume write-resume restarts a wr ite command that was sus- pended, and changes the suspend status bit in the sta- tus register (wse or wsp) back to ?0?. to execute a write-resume operation, the host drives ce# low, sends the write resume command cycle (30h), then drives ce# high. to determine if the inter- nal, self-timed write oper ation completed, poll the busy bit in the status regist er, or wait the specified time t se , t be or t pp for sector-erase, block-erase, or page-programming, respectively. the total write time before suspend and after resume will not exceed the uninterrupted write times t se , t be or t pp . 5.26 read security id the read security id operation is supported in both spi and sqi modes. to execute a read security id (sid) operation in spi mode, the host drives ce# low, sends the read security id command cycle (88h), two address cycles, and then one dummy cycle. to execute a read security id operation in sqi mode, the host drives ce# low and then sends the read security id command, two address cycles, and three dummy cycles. after the dummy cycles, the device outputs data on the falling edge of the sck signal, starting from the speci- fied address location. the data output stream is contin- uous through all sid addresses until terminated by a low-to-high transition on ce#. see table 5-5 for the security id address range. 5.27 program security id the program security id instruction programs one to 2040 bytes of data in the user-programmable, security id space. this security id space is one-time program- mable (otp). the device ignores a program security id instruction pointing to an invalid or protected address, see table 5-5 . prior to the program operation, execute wren. to execute a program sid operation, the host drives ce# low, sends the program security id command cycle (a5h), two address cycles, the data to be pro- grammed, then drives ce# high. the programmed data must be between 1 to 256 bytes and in whole byte increments. the device handles shifting of more than 256 bytes of data by maintaining the last 256 bytes of data as the correct data to be programmed. if the target address for the program security id instruction is not the beginning of the page boundary, and the number of data input exceeds or overlaps the end of the address of the page boundary, the excess data inputs wrap around and will be programmed at the start of that target page. the program security id operation is supported in both spi and sqi mode. to determine the completion of the internal, self-timed program sid operation, poll the busy bit in the software status register, or wait t psid for the completion of the internal self-timed program security id operation. table 5-5: program security id program security id address range unique id pre-programmed at factory 0000 ? 0007h user programmable 0008h ? 07ffh
sst26vf016b ds20005262c-page 30 ? 2014-2015 microchip technology inc. 5.28 lockout security id the lockout security id instruction prevents any future changes to the security id, and is supported in both spi and sqi modes. prior to the operation, execute wren. to execute a lockout sid, the host drives ce# low, sends the lockout security id command cycle (85h), then drives ce# high. poll the busy bit in the software status register, or wait t psid, for the completion of the lockout security id operation. 5.29 read-status register (rdsr) and read-configuration register (rdcr) the read-status register (rdsr) and read-configu- ration register (rdcr) commands output the contents of the status and configurat ion registers. these com- mands function in both spi and sqi modes. the status register may be read at any time, even during a write operation. when a write is in progress, poll the busy bit before sending any new commands to assure that the new commands are properly received by the device. to read the status or config uration registers, the host drives ce# low, then sends the read-status-register command cycle (05h) or the read confi guration reg- ister command (35h). a dummy cycle is required in sqi mode. immediately afte r the command cycle, the device outputs data on the falling edge of the sck sig- nal. the data output stream continues until terminated by a low-to-high transition on ce#. see figures 5-28 and 5-29 for the instruction sequence. figure 5-28: read-status-register and read-configuration register sequence (sqi) figure 5-29: read-status-register and read-configuration register sequence (spi) 20005262 f11.0 mode 3 0 sck sio(3:0) ce# c1 c0 mode 0 2 xx msn lsn 4 h0 l0 6 h0 l0 8 h0 l0 d u mmy statu s byte stat u s byte stat u s byte note: msn = most significant nibble; lsn = leas t significant nibble, c[1:0]=05h or 35h 0123456 7 8 9 1011121314 20005262 f62.1 mode 3 sck si so ce# bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05 or 35h mode 0 high impedance status or configu ration register out msb msb
? 2014-2015 microchip technology inc. ds20005262c-page 31 sst26vf016b 5.30 write-status register (wrsr) the write-status register (wrsr) command writes new values to the configuration register. to execute a write-status register opera tion, the host drives ce# low, then sends the write- status register command cycle (01h), two cycles of data, and then drives ce# high. values in the second data cycle will be accepted by the device. see figures 5-30 and 5-31 . figure 5-30: write-status- register sequence (sqi) figure 5-31: write-status- register sequence (spi) 20005262 f63.1 mode 3 0 1 sck sio[3:0] ce# c1 c0 mode 0 2 h0 l0 msn lsn 4 h0 l0 5 3 statu s byte command config- u ration byte note: msn = most significant nibble; lsn = least si gnificant nibble, xx = don?t care, c[1:0]=01h 20005262 f64.1 mode 3 high impedance mode 0 s tat u s register 76543210 msb msb msb 01 mode 3 sck si so ce# mode 0 06 01234567 01234567 8 9 101112131415 configuration register 76543210 msb 16 17 1 8 19 20 21 22 23 note: xx = don?t care
sst26vf016b ds20005262c-page 32 ? 2014-2015 microchip technology inc. 5.31 write-enable (wren) the write enable (wren) instruction sets the write- enable-latch bit in the status register to ?1,? allowing write operations to occur. the wren instruction must be executed prior to any of the following operations: sector erase, block erase, chip erase, page program, program security id, lockout security id, write block- protection register, lock-down block-protection reg- ister, non-volatile write-lock lock-down register, spi quad page program, and write-status register. to execute a write enable the host drives ce# low then sends the write enable command cycle (06h) then drives ce# high. see figures 5-32 and 5-33 for the wren instruction sequence. figure 5-32: write-enable sequence (sqi) figure 5-33: write-e nable sequence (spi) 20005262 f12.1 mode 3 0 1 sck sio[3:0] ce# 06 mode 0 ce# so si sck 01234567 06 high impedance mode 0 mode 3 20005262 f18.0 msb
? 2014-2015 microchip technology inc. ds20005262c-page 33 sst26vf016b 5.32 write-disable (wrdi) the write-disable (wrdi) in struction sets the write- enable-latch bit in the status register to ?0,? preventing write operations. the wrdi instruction is ignored during any internal write operations. any write opera- tion started before executing wrdi will complete. drive ce# high before executing wrdi. to execute a write-disable, the host drives ce# low, sends the write disable command cycle (04h), then drives ce# high. see figures 5-34 and 5-35. figure 5-34: write-disabl e (wrdi) sequence (sqi) figure 5-35: write-disabl e (wrdi) sequence (spi) 20005262 f33.1 mode 3 0 1 sck sio(3:0) ce# 04 mode 0 ce# so si sck 01234567 04 high impedance mode 0 mode 3 20005262 f19.0 msb
sst26vf016b ds20005262c-page 34 ? 2014-2015 microchip technology inc. 5.33 read block-protection register (rbpr) the read block-protection register instruction outputs the block-protection register data which determines the protection status. to execute a read block-protec- tion register operation, the host drives ce# low, and then sends the read block-protection register com- mand cycle (72h). a dummy cycle is required in sqi mode. after the command cycle, the device outputs data on the falling edge of the sck signal starting with the most significant bit(s), see table 5-6 for definitions of each bit in the block-protection register. the rbpr command does not wrap around. after all data has been output, the device will output 0h until terminated by a low-to- high transition on ce#. figures 5-36 and 5-37 . figure 5-36: read block-protec tion register sequence (sqi) figure 5-37: read block-protection register sequence (spi) 20005262 f34.2 mode 3 0 sck sio[3:0] ce# c1 c0 2 h0 l0 msn lsn 4 h1 l1 6 h2 l2 8 h3 l3 10 h4 l4 12 hn ln bpr [m:m-7] bpr [7:0] xx note: msn = most significant nibble, lsn = least significant nibble block-protection register (bpr), m = 47 for sst26vf016b, c[1:0]=72h ce# sio0 sck 012345678 32 33 24 mode 3 mode 0 15 16 23 72h 20005262 f65.1 sio op code data byte 0 data byte 1 data byte 2 data byte n
? 2014-2015 microchip technology inc. ds20005262c-page 35 sst26vf016b 5.34 write block-protection register (wbpr) the write block-protection register (wbpr) com- mand changes the block-protection register data to indicate the protection status. execute wren before executing wbpr. to execute a write block-protection register operation the host drives ce# low, s ends the write block-protec- tion register command cycle (42h), sends 18 cycles of data, and finally drives ce# high. data input must be most significant bit(s) first. see table 5-6 for definitions of each bit in the block-protection register. see figures 5-38 and 5-39 . figure 5-38: write bl ock-protection regi ster sequence (sqi) figure 5-39: write bl ock-protection regi ster sequence (spi). mode 3 0 sck sio(3:0) ce# c1 c0 mode 0 2 h0 l0 msn lsn 4 h1 l1 6 h2 l2 8 h3 l3 10 h4 l4 12 h5 l5 hn ln bpr [m:m-7] bpr [7:0] note: msn = most significant nibble, lsn = least significant nibble block-protection register (bpr) m = 47, c[1:0]=42h. ce# so si sck data byte0 01234567 8 data byte1 data byte2 data byten 42h 15 16 23 24 31 32 mode 0 mode 3 op code 20005262 f66.1 note: c[1:0]=42h
sst26vf016b ds20005262c-page 36 ? 2014-2015 microchip technology inc. 5.35 lock-down block-protection register (lbpr) the lock-down block-protection register instruction prevents changes to the block-protection register during device operation. lock-down resets after power cycling; this allows the block-protection register to be changed. execute wren before initiating the lock- down block-protection register instruction. to execute a lock-down bloc k-protection register, the host drives ce# low, then sends the lock-down block- protection register command cycle (8dh), then drives ce# high. figure 5-40: lock-down blo ck-protection register (sqi) figure 5-41: lock-down block- protection register (spi) 20005262 f30.1 mode 3 0 1 sck sio(3:0) ce# c1 c0 mode 0 note: c[1:0]=8dh 20005262 f67.0 mode 3 0 1 sck sio0 ce# mode 0 234567 8d sio[3:1]
? 2014-2015 microchip technology inc. ds20005262c-page 37 sst26vf016b 5.36 non-volatile write-lock lock- down register (nvwldr) the non-volatile write-lock lock-down register (nvwldr) instruction controls the ability to change the write-lock bits in the block-protection register. exe- cute wren before initiating the nvwldr instruction. to execute nvwldr, the host drives ce# low, then sends the nvwldr command cycle (e8h), followed by 18 cycles of data, and then drives ce# high. after ce# goes high, the non-volatile bits are pro- grammed and the programming time-out must com- plete before any additional commands, other than read status register, can be entered. poll the busy bit in the status register, or wait t pp , for the completion of the internal, self-timed, write operation. data inputs must be most significant bit(s) first. figure 5-42: write-l ock lock-down register sequence (sqi) figure 5-43: write-l ock lock-down regist er sequence (spi) 20005262 f36.0 mode 3 0 sck sio(3:0) ce# e 8 mode 0 2 h0 l0 msn lsn 4 h1 l1 6 h2 l2 8 h3 l3 10 h4 l4 12 h5 l5 hn ln n vwldr[m:m-7] bpr [7:0] note: msn= most significant nibble; lsn = least significant nibble write-lock lock-down register (nvwldr) m = 47 ce# so si sck data byte0 01234567 8 data byte1 data byte2 data byten e8h 15 16 23 24 31 32 mode 0 mode 3 op code 20005262 f69.1
sst26vf016b ds20005262c-page 38 ? 2014-2015 microchip technology inc. 5.37 global block-protection unlock (ulbpr) the global block-protection unlock (ulbpr) instruc- tion clears all write-protection bits in the block-protec- tion register, except for those bits that have been locked down with the nvwldr command. execute wren before initiating the ulbpr instruction. to execute a ulbpr instruct ion, the host drives ce# low, then sends the ulbpr command cycle (98h), and then drives ce# high. figure 5-44: global block-protection unlock (sqi) figure 5-45: global block-protection unlock (spi) 20005262 f20.1 mode 3 0 1 sck sio(3:0) ce# c1 c0 mode 0 note: c[1:0]=98h 20005262 f68.0 mode 3 0 1 sck sio0 ce# mode 0 234567 98 sio[3:1]
? 2014-2015 microchip technology inc. ds20005262c-page 39 sst26vf016b table 5-6: block-protection register for sst26vf016b 1 bpr bits address range protected block size read lock write lock/nvwldr 2 47 46 1fe000h - 1fffffh 8 kbyte 45 44 1fc000h - 1fdfffh 8 kbyte 43 42 1fa000h - 1fbfffh 8 kbyte 41 40 1f8000h - 1f9fffh 8 kbyte 39 38 006000h - 007fffh 8 kbyte 37 36 004000h - 005fffh 8 kbyte 35 34 002000h - 003fffh 8 kbyte 33 32 000000h - 001fffh 8 kbyte 31 1f0000h - 1f7fffh 32 kbyte 30 008000h - 00ffffh 32 kbyte 29 1e0000h - 1effffh 64 kbyte 28 1d0000h -1dffffh 64 kbyte 27 1c0000h -1cffffh 64 kbyte 26 1b0000h - 1bffffh 64 kbyte 25 1a0000h - 1affffh 64 kbyte 24 190000h - 19ffffh 64 kbyte 23 180000h - 18ffffh 64 kbyte 22 170000h - 17ffffh 64 kbyte 21 160000h - 16ffffh 64 kbyte 20 150000h - 15ffffh 64 kbyte 19 140000h - 14ffffh 64 kbyte 18 130000h - 13ffffh 64 kbyte 17 120000h - 12ffffh 64 kbyte 16 110000h - 11ffffh 64 kbyte 15 100000h - 10ffffh 64 kbyte 14 0f0000h - 0fffffh 64 kbyte 13 0e0000h - 0effffh 64 kbyte 12 0d0000h - 0dffffh 64 kbyte 11 0c0000h - 0cffffh 64 kbyte 10 0b0000h - 0bffffh 64 kbyte 9 0a0000h - 0affffh 64 kbyte 8 090000h - 09ffffh 64 kbyte 7 080000h - 08ffffh 64 kbyte 6 070000h - 07ffffh 64 kbyte 5 060000h - 06ffffh 64 kbyte 4 050000h - 05ffffh 64 kbyte 3 040000h - 04ffffh 64 kbyte 2 030000h - 03ffffh 64 kbyte 1 020000h - 02ffffh 64 kbyte 0 010000h - 01ffffh 64 kbyte 1. the default state after a power-on reset is write-protected bpr[47:0] = 5555 ffff ffff 2. nvwldr bits are one-time-programmable. once a wlldr bit is set, the protection state of that particular block is permanently write-locked.
sst26vf016b ds20005262c-page 40 ? 2014-2015 microchip technology inc. 5.38 deep power-down the deep power-down (dpd ) instruction puts the device in the lowest power consumption mode?the deep power-down mode. the deep power-down instruction is ignored during an internal write operation. while the device is in deep power-down mode, all instructions will be ignored except for the release deep power-down instruction. enter deep power-down mode by initiating the deep power-down (dpd) instruction (b9h) while driving ce# low. ce# must be driven high before executing the dpd instruction. after ce# is driven high, it requires a delay of t dpd before the standby current i sb is reduced to deep power-down current i dpd . see table 5-7 for deep power-down timing. if the device is busy perform- ing an internal erase or program operation, initiating a deep power-down instruction will not placed the device in deep power-down mode. see figures 5-46 and 5-47 for the dpd instruction sequence. figure 5-46: deep power-down (dpd) sequence?sqi mode figure 5-47: deep power- down (dpd)?spi mode table 5-7: deep power-down symbol parameter min max units tdpd ce# high to deep power-down 3 s tsbr ce# high to standby mode 10 s 20005262 f100.0 mode 3 sck sio(3:0) ce# mode 0 b9 msn lsn 0 1 t dpd standb y mode deep po w er-do wn mode note: msn= most significant nibble; lsn = least significant nibble ce# so si sck 01234567 b9 high impedance mode 0 mode 3 20005262 f101.0 msb t dpd standb y mode deep po w er-do wn mode
? 2014-2015 microchip technology inc. ds20005262c-page 41 sst26vf016b 5.39 release from deep power-down and read id release from deep power-down (rdpd) and read id instruction exits deep power-down mode. to exit deep power down mode, execute the rdpd. during this command, the host drives ce # low, then sends the deep power-down command cycle (abh), and then drives ce# high. the device will return to standby mode and be ready for the next instruction after t sbr . to execute rdpd and read the device id, the host drives ce# low then sends the deep power-down command cycle (abh), thre e dummy clock cycles, and then drives ce# high. the device outputs the device id on the falling edge of the sck signal following the dummy cycles. the data outp ut stream is continuous until terminated by a low-to-high transition on ce, and will return to standby mode and be ready for the next instruction after t sbr . see figures 5-48 and 5-49 for the command sequence. figure 5-48: release from deep power-down (rdpd) and read id sequence?sqi mode figure 5-49: release from deep power-down (rdpd) and read id sequence?spi mode 20005262 f102.0 mode 3 0 sck sio[3:0] ce# c1 c0 mode 0 1 x x d1 d0 xx xx t sbr standb y mode deep po w er-do wn mode op code msn lsn de v ice id note: c[1:0]=abh 20005262 f103.0 mode 3 0 sck sio[3:0] ce# mode 0 t sbr standb y mode deep po w er-do wn mode op code de v ice id 15 16 23 24 32 33 40 1 2 3 4 5 6 7 8 ab xx xx xx
sst26vf016b ds20005262c-page 42 ? 2014-2015 microchip technology inc. 6.0 electrical specifications 6.1 power-up specifications all functionalities and dc sp ecifications are specified for a v dd ramp rate of greater than 1v per 100 ms (0v to 3.0v in less than 300 ms). see table 6-3 and figure 6-1 for more information. when v dd drops from the operating voltage to below the minimum v dd threshold at power-down, all opera- tions are disabled and the device does not respond to commands. data corruption may result if a power-down occurs while a write-registers, program, or erase operation is in progress. see figure 6-2 . absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maxi- mum stress ratings? may cause permanent damage to the device. this is a stress rating only and func- tional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. output shorted for no more than one second. n o more than one output shorted at a time. table 6-1: operating range range ambient temp v dd industrial -40c to +85c 2.7-3.6v extended -40c to +105c table 6-2: ac conditions of test 1 1. see figure 8-5 input rise/fall time output load 3ns c l = 30 pf table 6-3: recommended system power-up/down timings symbol parameter minimum max units condition t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. v dd min to read operation 100 s t pu-write 1 v dd min to write operation 100 s t pd 1 power-down duration 100 ms v off v dd off time 0.3 v 0v recommended
? 2014-2015 microchip technology inc. ds20005262c-page 43 sst26vf016b figure 6-1: power-up timing diagram figure 6-2: power-down and voltage drop diagram time v dd min v dd max v dd de vice fully accessib le t pu-read t pu-write chip selection is not allo w ed. commands may not b e accepted or properly interpreted b y the de v ice. 20005262 f27.0 de vice access allo w ed t pd t pu no de vice access allo w ed time v dd min v dd max v dd 20005262 f72.0 v off
sst26vf016b ds20005262c-page 44 ? 2014-2015 microchip technology inc. 7.0 dc characteristics table 7-1: dc operating characteristics (v dd = 2.3-3.6v) symbol parameter limits test conditions min typ max units i ddr1 read current 815ma v dd= v dd max, ce#=0.1 v dd /0.9 v dd @40 mhz, so=open i ddr2 read current 20 ma v dd = v dd max, ce#=0.1 v dd /0.9 v dd @104 mhz, so=open i ddw program and erase cur- rent 25 ma v dd max i sb standby current 15 45 a ce#=v dd , v in =v dd or v ss i dpd deep power-down cur- rent 825a ce#=v dd , v in =v dd or v ss i li input leakage current 2a v in =gnd to v dd , v dd =v dd max i lo output leakage current 2a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ih input high voltage 0.7 v dd v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min table 7-2: capacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c out 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. output pin capacitance v out = 0v 8 pf c in 1 input capacitance v i n = 0v 6 pf table 7-3: reliability characteristics symbol parameter minimum specification units test method n end 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. endurance 100,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lth 1 latch up 100 + i dd ma jedec standard 78 table 7-4: write timing parameters (v dd = 2.3-3.6v) symbol parameter minimum maximum units t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 50 ms t pp 1 1. estimate for typical condi tions less than 256 bytes: programming time (s) = 55 + (3.75 x # of bytes) page-program 1.5 ms t psid program security-id 1.5 ms t ws write-suspend latency 25 s t wpen write-protection enable bit latency 25 ms
? 2014-2015 microchip technology inc. ds20005262c-page 45 sst26vf016b 8.0 ac characteristics figure 8-1: hold timing diagram table 8-1: ac operating characteristics (v dd 1 = 2.3-3.6v) 1. maximum operating frequency for 2.7-3.6v is 104 mhz and for 2.3-3.6v is 80 mhz. symbol parameter limits - 40 mhz limits - 80 mhz limits - 104 mhz units min max min max min max f clk serial clock frequency 40 80 104 mhz t clk serial clock period 25 12.5 9.6 ns t sckh serial clock high time 11 5.5 4.5 ns t sckl serial clock low time 11 5.5 4.5 ns t sckr 2 2. maximum rise and fall time may be limited by t sckh and t sckl requirements serial clock rise time (slew rate) 0.1 0.1 0.1 v/ns t sckf 2 serial clock fall time (slew rate) 0.1 0.1 0.1 v/ns t ces 3 3. relative to sck. ce# active setup time 855ns t ceh 3 ce# active hold time 855ns t chs 3 ce# not active setup time 855ns t chh 3 ce# not active hold time 855ns t cph ce# high time 25 12.5 12 ns t chz ce# high to high-z output 19 12.5 12 ns t clz sck low to low-z output 000ns t hls hold# low setup time 855ns t hhs hold# high setup time 855ns t hlh hold# low hold time 855ns t hhh hold# high hold time 855ns t hz hold# low-to-high-z output 888ns t lz hold# high-to-low-z output 888ns t ds data in setup time 333ns t dh data in hold time 444ns t oh output hold from sck change 000ns t v output valid from sck 8/5 4 4. 30 pf/10 pf 8/5 4 8/5 4 ns t hz t lz t hhh t hls t hhs 20005262 f104.0 hold# ce# sck so si t hlh
sst26vf016b ds20005262c-page 46 ? 2014-2015 microchip technology inc. figure 8-2: serial input timing diagram figure 8-3: serial output timing diagram figure 8-4: reset timing diagram table 8-2: reset timing parameters t r(i) parameter minimum maximum units t r(o) reset to read (non-data operation) 20 ns t r(p) reset recovery from program or suspend 100 s t r(e) reset recovery from erase 1ms ce# sio[3:0] sck msb lsb t ds t dh t chh t ces t ceh t chs t sckr t sckf t cph 20005262 f105.0 20005262 f106.0 ce# sio[3:0] sck msb t clz t v t sckh t chz t oh t sckl lsb 20005262 f14.0 mode 3 clk sio(3:0) ce# mode 3 c1 c3 c2 c0 mode 0 mode 3 mode 0 mode 0 t cph note: c[1:0] = 66h; c[3:2] = 99h
? 2014-2015 microchip technology inc. ds20005262c-page 47 sst26vf016b figure 8-5: ac input/output reference waveforms 20005262 f28.0 reference points output input v ht v lt v ht v lt v iht v ilt ac test inputs are driven at v iht (0.9v dd ) for a logic ?1? and v ilt (0.1v dd ) for a logic ?0?. measure- ment reference points for inputs and outputs are v ht (0.6v dd ) and v lt (0.4v dd ). input rise and fall times (10% ? 90%) are <3 ns. note: v ht - v high te s t v lt - v low te s t v iht - v input high test v ilt - v input low test
sst26vf016b ds20005262c-page 48 ? 2014-2015 microchip technology inc. 9.0 packaging information 9.1 package marking legend: xx...x part number or part number code y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec ? designator for matte tin (sn) note : for very small packages with no room for the pb-free jedec ? designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part num ber cannot be marked on one line, it will be carried over to the next line, th us limiting the number of available characters for custom er-specific information. 3 e 3 e part number 1st line marking codes soij soic wdfn sst26vf016b 26f016b 26f016b 26f016b 8-lead soij (5.28 mm) example 8-lead soic (3.90 mm) example nnn 3 e 1503343 26f016b sn1503 343 xxxxxxxx yywwnnn xxxxxxxx mf 1503343 26f016b 8-lead wdfn (5x6 mm) example
? 2014-2015 microchip technology inc. ds20005262c-page 49 sst26vf016b 9.2 packaging diagrams b a 0.15 c 0.15 c d2 e2 8 x b 0.10 c a b 0.05 c (datum b) (datum a) c seating plane note 1 2x bottom view microchip technology drawing c04-210b sheet 1 of 2 for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: n 0.10 c a b 0.10 c a b a3 0.10 c 0.08 c a1 d e note 1 2x a 12 12 e see detail a side view top view n k 8-lead plastic very, very thin small outline no-lead (mf) - 5x6 mm body [wdfn]
sst26vf016b ds20005262c-page 50 ? 2014-2015 microchip technology inc. microchip technology drawing c04-210b sheet 2 of 2 for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: e/2 e l (datum a) detail a 8-lead plastic very, very thin small outline no-lead (mf) - 5x6 mm body [wdfn] number of terminals overall height terminal width overall width overall length terminal length exposed pad width exposed pad length terminal thickness pitch standoff units dimension limits a1 a b e d2 e2 a3 e l d n 1.27 bsc 0.20 ref 0.50 0.35 0.70 0.00 0.42 6.00 bsc 0.60 3.40 bsc 4.00 bsc 0.75 0.02 5.00 bsc millimeters min nom 8 0.70 0.48 0.80 0.05 max k- 0.20 - ref: reference dimension, usually without tolerance, for information purposes only. bsc: basic dimension. theoretically exact value shown without tolerances. 1. 2. 3. notes: pin 1 visual index feature may vary, but must be located within the hatched area. package is saw singulated dimensioning and tolerancing per asme y14.5m terminal-to-exposed-pad
? 2014-2015 microchip technology inc. ds20005262c-page 51 sst26vf016b note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
sst26vf016b ds20005262c-page 52 ? 2014-2015 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2014-2015 microchip technology inc. ds20005262c-page 53 sst26vf016b note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
sst26vf016b ds20005262c-page 54 ? 2014-2015 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2014-2015 microchip technology inc. ds20005262c-page 55 sst26vf016b table 9-1: revision history revision description date a ? initial release of data sheet may 2014 b ? removed the sst26vf016ba device from the data sheet ? added part markings feb 2015 c ? extended the voltage range ? added extended temperature range. aug 2015
sst26vf016b ds20005262c-page 56 ? 2014-2015 microchip technology inc. the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by us ing your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of micro- chip sales offices, distributors and factory repre- sentatives customer change notification service microchip?s customer noti fication service helps keep customers current on microc hip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. to register, access the microchip web site at www.micro- chip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip produc ts can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact thei r distributor, representa- tive or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
? 2014-2015 microchip technology inc. ds20005262c-page 57 sst26vf016b 10.0 product iden tification system to order or obtain information, e.g., on pricing or deli very, refer to the factory or the listed sales office. part no. xxx x operating device device: sst26vf016b = 16 mbit, 2.5v/3.0v, sqi flash memory wp#/hold# pin enable at power-up tape and reel flag: t = tape and reel (blank) = tube or tray operating frequency: 104 = 104 mhz temperature: i = -40c to +85c v = -40c to +105c package: mf = wdfn (6mm x 5mm body), 8-lead sm = soij (5.28 mm body), 8-lead sn = soic (3.90 mm body), 8-lead valid combinations: sst26vf016b-104i/sm sst26vf016bt-104i/sm sst26vf016b-104i/sn sst26vf016bt-104i/sn sst26vf016b-104i/mf sst26vf016bt-104i/mf sst26vf016b-104v/sm sst26vf016bt-104v/sm sst26vf016b-104v/sn sst26vf016bt-104v/sn sst26vf016b-104v/mf sst26vf016bt-104v/mf x tape/reel indicator frequency xx package temperature / ?
sst26vf016b ds20005262c-page 58 ? 2014-2015 microchip technology inc. 11.0 appendix table 11-1: serial flash discoverable parameter (sfdp) (1 of 16) address bit address data comments sfdp header sfdp header: 1 st dword 00h a7:a0 53h sfdp signature sfdp signature=50444653h 01h a15:a8 46h 02h a23:a16 44h 03h a31:a24 50h sfdp header: 2 nd dword 04h a7:a0 06h sfdp minor revision number 05h a15:a8 01h sfdp major revision number 06h a23:a16 02h number of parameter headers (nph)=3 07h a31:a24 ffh unused . contains ff and can not be changed. parameter headers jedec flash parameter header: 1 st dword 08h a7:a0 00h parameter id least sign ificant bit (lsb) number . when this field is set to 00h, it indicates a jedec-specified header. for vendor-specified headers, this field must be set to the vendor?s manufac- turer id. 09h a15:a8 06h parameter table minor revision number minor revisions are either clarificatio ns or changes that add parameters in existing reserved locations. minor revisions do not change overall structure of sfdp. minor revision starts at 00h. 0ah a23:a16 01h parameter table major revision number major revisions are changes that reorganize or add parameters to loca- tions that are not currently reserved. major revisions would require code (bios/firmware) or hardware change to get previously defined dis- coverable parameters. majo r revision starts at 01h 0bh a31:a24 10h parameter table length number of dwords that are in the parameter table jedec flash parameter header: 2 nd dword 0ch a7:a0 30h parameter table pointer (ptp) a 24-bit address that specifies the st art of this header?s parameter table in the sfdp structure. the address must be dword-aligned. 0dh a15:a8 00h 0eh a23:a16 00h 0fh a31:a24 ffh parameter id most significant bit (msb) number . jedec sector map parameter header: 3 rd dword 10h a7:a0 81h parameter id lsb number . sector map function-specific table is assigned 81h. 11h a15:a8 00h parameter table minor revision number minor revisions are either clarificatio ns or changes that add parameters in existing reserved locations. minor revisions do not change overall structure of sfdp. minor revision starts at 00h. 12h a23:a16 01h parameter table major revision number major revisions are changes that reorganize or add parameters to loca- tions that are not currently reserved. major revisions would require code (bios/firmware) or hardware change to get previously defined dis- coverable parameters. majo r revision starts at 01h
? 2014-2015 microchip technology inc. ds20005262c-page 59 sst26vf016b 13h a31:a24 06h parameter table length number of dwords that are in the parameter table jedec flash parameter header: 4 th dword 14h a7:a0 00h parameter table pointer (ptp) this 24-bit address specifies the start of this header?s parameter table in the sfdp structure. the addr ess must be dword-aligned. 15h a15:a8 01h 16h a23:a16 00h 17h a31:a24 ffh parameter id msb . microchip (vendor) parameter header: 5 th dword 18h a7:a0 bfh id number manufacture id (vendor specified header) 19h a15:a8 00h parameter table minor revision number 1ah a23:a16 01h parameter table major revision number, revision 1.0 1bh a31:a24 18h parameter table length, 24 double words microchip (vendor) parameter header: 6 th dword 1ch a7:a0 00h parameter table pointer (ptp) this 24-bit address specifies the start of this header?s parameter table in the sfdp structure. the addr ess must be dword-aligned. 1dh a15:a8 02h 1eh a23:a16 00h 1fh a31:a24 01h used to indicate bank number (vendor specific). jedec flash parameter table jedec flash parameter table: 1 st dword 30h a1:a0 fdh block/sector erase sizes 00: reserved 01: 4 kbyte erase 10: reserved 11: use this setting only if the 4 byte erase is unavailable. a2 write granularity 0: single-byte programmable devices or buffer programmable devices with buffer is less than 64 bytes (32 words). 1: for buffer programmable devices when the buffer size is 64 bytes (32 words) or larger. a3 volatile status register 0: target flash has nonvolatile st atus bit. write/erase commands do not require status register to be written on every power on. 1: target flash has a4 write enable opcode select for writing to volatile status register 0: 0x50. enables a status register write when bit 3 is set to 1. 1: 0x06 enables a status register write when bit 3 is set to 1 . a7:a5 unused . contains 111b and can not be changed 31h a15:a8 20h 4 kbyte erase opcode table 11-1: serial flash discoverable parameter (sfdp) (continued) (2 of 16) address bit address data comments
sst26vf016b ds20005262c-page 60 ? 2014-2015 microchip technology inc. 32h a16 f1h supports (1-1-2) fast read 0: (1-1-2) fast read n ot supported 1: (1-1-2) fast read supported a18:a17 address bytes number of bytes used in addressing flash array read, write and erase 00: 3-byte only addressing 01: 3- or 4-byte addressing (e.g. defaults to 3-byte mode; enters 4-byte mode on command) 10: 4-byte only addressing 11: reserved a19 supports double transfer rate (dtr) clocking indicates the device supports some ty pe of double transfer rate clocking. 0: dtr not supported 1: dtr clocking supported a20 supports (1-2-2) fast read device supports single input opcode, dual input address, and dual output data fast read. 0: (1-2-2) fast read n ot supported. 1: (1-2-2) fast read supported. a21 supports (1-4-4) fast read device supports single input opcode, quad input address, and quad out- put data fast read 0: (1-4-4) fast read n ot supported. 1: (1-4-4) fast read supported . a22 supports (1-1-4) fast read device supports single input opcode & address and quad output data fast read. 0: (1-1-4) fast read n ot supported. 1: (1-1-4) fast read supported . a23 unused . contains ?1? can not be changed. 33h a31:a24 ffh unused . contains ff can not be changed jedec flash parameter table: 2 nd dword 34h a7:a0 ffh flash memory density sst26vf016b = 00ffffffh 35h a15:a8 ffh 36h a23:a16 ffh 37h a31:a24 00h jedec flash parameter table: 3 rd dword 38h a4:a0 44h (1-4-4) fast read number of wait states (dummy clocks) needed before valid output 00100b: 4 dummy clocks (16 dummy bits) are needed with a quad input address phase instruction a7:a5 quad input address quad output (1 -4-4) fast read number of mode bits 010b: 2 dummy clocks (8 mode bits) are needed with a single input opcode, quad input address and quad ou tput data fast read instruction. 39h a15:a8 ebh (1-4-4) fast read opcode opcode for single input opcode, q uad input address, and quad output data fast read. table 11-1: serial flash discoverable parameter (sfdp) (continued) (3 of 16) address bit address data comments
? 2014-2015 microchip technology inc. ds20005262c-page 61 sst26vf016b 3ah a20:a16 08h (1-1-4) fast read number of wait states (dummy clocks) needed before valid output 01000b: 8 dummy bits are needed with a single input opcode & address and quad output data fast read instruction a23:a21 (1-1-4) fast read nu mber of mode bits 000b: no mode bits are needed with a single input opcode & address and quad output data fast read instruction 3bh a31:a24 6bh (1-1-4) fast read opcode opcode for single input opcode & address and quad output data fast read. jedec flash parameter table: 4 th dword 3ch a4:a0 08h (1-1-2) fast read number of wait states (dummy clocks) needed before valid output 01000b: 8 dummy clocks are needed with a single input opcode, address and dual output data fast read instruction. a7:a5 (1-1-2) fast read nu mber of mode bits 000b: no mode bits are needed with a single input opcode & address and quad output data fast read instruction 3dh a15:a8 3bh (1-1-2) fast read opcode opcode for single input opcode& address and dual output data fast read. 3eh a20:a16 80h (1-2-2) fast read number of wait states (dummy clocks) needed before valid output 00010b: 0 clocks of dummy cycle. a23:a21 (1-2-2) fast read number of mode bits (in clocks) 010b: 4 clocks of mode bits are needed 3fh a31:a24 bbh (1-2-2) fast read opcode opcode for single input opcode, dual input address, and dual output data fast read. jedec flash parameter table: 5 th dword 40h a0 feh supports (2-2-2) fast read device supports dual input opcode& address and dual output data fast read. 0: (2-2-2) fast read not supported. 1: (2-2-2) fast read supported. a3:a1 reserved . bits default to all 1?s. a4 supports (4-4-4) fast read device supports quad input opcode & address and quad output data fast read. 0: (4-4-4) fast read n ot supported. 1: (4-4-4) fast read supported. a7:a5 reserved. bits default to all 1?s. 41h a15:a8 ffh reserved . bits default to all 1?s. 42h a23:a16 ffh reserved . bits default to all 1?s. 43h a31:a24 ffh reserved . bits default to all 1?s. table 11-1: serial flash discoverable parameter (sfdp) (continued) (4 of 16) address bit address data comments
sst26vf016b ds20005262c-page 62 ? 2014-2015 microchip technology inc. jedec flash parameter table: 6 th dword 44h a7:a0 ffh reserved . bits default to all 1?s. 45h a15:a8 ffh reserved . bits default to all 1?s. 46h a20:a16 00h (2-2-2) fast read number of wait states (dummy clocks) needed before valid output 00000b: no dummy bit is needed a23:a21 (2-2-2) fast read nu mber of mode bits 000b: no mode bits are needed 47h a31:a24 ffh (2-2-2) fast read opcode opcode for dual input opcode& addres s and dual output data fast read. (not supported) jedec flash parameter table: 7 th dword 48h a7:a0 ffh reserved . bits default to all 1?s. 49h a15:a8 ffh reserved . bits default to all 1?s. 4ah a20:a16 44h (4-4-4) fast read number of wait states (dummy clocks) needed before valid output 00100b: 4 clocks dummy are needed with a quad input opcode & address and quad output data fast read instruction a23:a21 (4-4-4) fast read nu mber of mode bits 010b: 2 clocks mode bits are needed with a quad input opcode & address and quad output data fast read instruction 4bh a31:a24 0bh (4-4-4) fast read opcode opcode for quad input opcode/addres s, quad output data fast read jedec flash parameter table: 8 th dword 4ch a7:a0 0ch sector type 1 size 4 kbyte, sector/block size = 2 n bytes 4dh a15:a8 20h sector type 1 opcode opcode used to erase the number of bytes specified by sector type 1 size 4eh a23:a16 0dh sector type 2 size 8 kbyte, sector/block size = 2 n bytes 4fh a31:a24 d8h sector type 2 opcode opcode used to erase the number of bytes specified by sector type 2 size jedec flash parameter table: 9 th dword 50h a7:a0 0fh sector type 3 size 32 kbyte, sector/block size = 2 n bytes 51h a15:a8 d8h sector type 3 opcode opcode used to erase the number of bytes specified by sector type 3 size 52h a23:a16 10h sector type 4 size 64 kbyte, sector/block size = 2 n bytes 53h a31:a24 d8h sector type 4 opcode opcode used to erase the number of bytes specified by sector type 4 size table 11-1: serial flash discoverable parameter (sfdp) (continued) (5 of 16) address bit address data comments
? 2014-2015 microchip technology inc. ds20005262c-page 63 sst26vf016b jedec flash parameter table: 10 th dword 54h a3:a0 20h multiplier from typical erase time to maximum erase time maximum time = 2*(count + 1)*typical erase time count = 0 a3:a0= 0000b a7:a4 erase type 1 erase, typical time typical time = (count +1)*units 1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s 10:9 units ( 00b:1ms , 01b: 16ms, 10b:128ms, 11b:1s) a8:a4 count = 18 = 10010b a10:a9 unit = 1ms = 00b 55h a10:a8 91h a10:a8=001b a15:a11 erase type 2 erase, typical time typical time = (count+1)*units 1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s 17:16 units ( 00b:1ms , 01b:16ms, 10b:128ms, 11b:1s) a15:a11 count = 18 =10010b a17:a16 unit = 1ms =00b 56h a17:a16 48h a17:a16=00b a23:a18 erase type 3 erase, typical time typical time = (count+1)*units 1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s 24:23 units ( 00b: 1ms , 01b: 16ms, 10b:128ms, 11b:1s) a22:a18 count = 18 = 10010b a24:a23 unit = 1ms = 00b 57h a24 24h a24=0b a31:a25 erase type 4 erase, typical time typical time = (count+1)*units 1ms to 32ms, 16ms to 512ms, 128ms to 4096ms, 1s to 32s 31:30 units ( 00b: 1ms , 01b: 16ms, 10b:128ms, 11b:1s) a29:a25 count=18=10010b a31:a30 unit = 1ms =00b jedec flash parameter table: 11 th dword 58h a3:a0 80h multiplier from typical progra m time to maximum program time maximum time = 2*(count +1)*typical program time. count =0 a3:a0=0000b a7:a4 page size page size = 2 n bytes. n=8 a7:a4 =1000b 59h a13:a8 6fh page program typical time program time = (count+1)*units 13 units (0b: 8s, 1b: 64s ) a12:a8 count=11 = 01111b a13 unit = 64s = 1b a15:a14 byte program typical time, first byte typical time = (count+1)*units 18 units (0b: 1s, 1b: 8s ) a17:a14 count = 5 = 0101b a18 =8s=1b table 11-1: serial flash discoverable parameter (sfdp) (continued) (6 of 16) address bit address data comments
sst26vf016b ds20005262c-page 64 ? 2014-2015 microchip technology inc. 5ah a18:a16 1dh a18:a16=101b a23:a19 byte program typical time, additional byte typical time = (count+1)*units 23 units ( 0b: 1s , 1b: 8s) a22:a19 count = 0011b a23=1 s=0b 5bh a30:a:24 81h chip erase typical time typical time = (count+1)*units 16ms to 512ms, 256ms to 8192ms, 4s to 128s, 64s to 2048s a28:a24 count =1=00001b a30:a29 units =16ms=00b a31 reserved a31=1b jedec flash parameter table: 12 th dword 5ch a3:a0 edh prohibited operations during program suspend xxx0b: may not initiate a new erase anywhere xxx1b:may not initiate a new erase in the program suspended page size xx0xb:may not initiate a new page program anywhere xx1xb: may not initiate a new page pr ogram in program suspended page size. x0xxb:refer to the data sheet x1xxb: may not initiate a read in the program suspended page size 0xxxb: additional erase or program restrictions apply 1xxxb: the erase and program restrictions in bits 1:0 are sufficient a7:a4 prohibited operation during erase suspend xxx0b: may not initiate a new erase anywhere xxx1b:may not initiate a new erase in the erase suspended page size xx0xb:may not initiate a new page program anywhere xx1xb: may not initiate a new page program in erase suspended erase type size. x0xxb:refer to the data sheet x1xxb: may not initiate a read in the erase suspended page size 0xxxb: additional erase or program restrictions apply 1xxxb: the erase and program restrictions in bits 5:4 are sufficient 5dh a8 0fh reserved = 1b a12:a9 program resume to suspend interval the device requires this typical am ount of time to make progress on the program operation before allowing another suspend. interval =500s program resume to suspend interval =(count+1)*64s a12:a9= 7 = 0111b a15:a13 suspend in-progress program max latency maximum time required by the flash device to suspend an in-progress program and be ready to accept another command which accesses the flash array. max latency = 25s program max latency =(count+1)*units units (00b:128ns, 01b:1s , 10b:8s, 11b:64s) a17:a13= count = 24 = 11000b a19:a18 = 1s =01b table 11-1: serial flash discoverable parameter (sfdp) (continued) (7 of 16) address bit address data comments
? 2014-2015 microchip technology inc. ds20005262c-page 65 sst26vf016b 5eh a19:a16 77h 0111b a23:a20 erase resume to suspend interval the device requires this typical am ount of time to make progress on the erase operation before allowing another suspend. interval = 500s erase resume to suspend interval =(count+1)*64s a23:a20= 7 = 0111b 5fh a30:a24 38h suspend in-progress erase max latency maximum time required by the flash device to suspend an in-progress erase and be ready to accept anot her command which accesses the flash array. max latency = 25s erase max latency =(count+1)*units units (00b:128ns, 01b:1s , 10b:8s, 11b:64s) a28:a24= count = 24 = 11000b a30:a29 = 1s =01b a31 suspend/resume supported 0:supported 1:not supported jedec flash parameter table: 13 th dword 60h a7:a0 30h program resume instruction 61h a15:a8 b0h program suspend instruction 62h a23:a16 30h resume instruction 63h a31:a24 b0h suspend instruction jedec flash parameter table: 14 th dword 64h a1:a0 f7h reserved = 11b a7:a2 status register polling device busy 1111 01b: use of legacy polling is supporte d by reading the status register with 05h instruction and checking wip bit [0] (0=ready, 1=busy) 65h a14:a8 a9h exit deep power-down to next operation delay:10s delay = (count+1)*unit a12:a8 = count = 9 = 01001b a14:a13 units = 01b = 1s a15 exit power-down instruction: abh = 10101011b a15 = 1b 66h a22:a16 d5h a22:a16 = 1010101b a23 enter power-down instruction: b9h = 10111001b a23 = 1b 67h a30:a24 5ch a30:a24 = 1011100 a31 deep power-down supported 0:supported 1:not supported jedec flash parameter table: 15 th dword 68h a3:a0 29h 4-4-4 mode disable sequences xxx1b: issue ff instruction 1xxxb: issue the soft reset 66/99 sequence. a7:a4 4-4-4 mode enable sequences x_xx1xb: issue instruction 38h table 11-1: serial flash discoverable parameter (sfdp) (continued) (8 of 16) address bit address data comments
sst26vf016b ds20005262c-page 66 ? 2014-2015 microchip technology inc. 69h a8 c2h 4-4-4 mode enable sequences a8 = 0 a9 0-4-4 mode supported 0:not supported 1:supported a15:a10 0-4-4 mode exit method x1_xxxx:mode bit[7:0] not= axh 1x_xxxx reserved = 1 6ah a19:a16 5ch 0-4-4 mode entry method x1xxb: m[7:0]=axh 1xxxb:reserved =1 a22:a20 quad enable requirements (qer) 101b: quad enable is bit 1 of the configuration register. a23 hold and reset disable 0:feature is not supported 6bh a31:a24 ffh reserved bits = 0xff jedec flash parameter table: 16 th dword 6c a6:a0 f0h volatile or non-volatile register and write enable instructions for status register 1 xx1_xxxxb:status register 1 contains a mix of volatile and non-volatile bits. the 06h instruction is used to enable writing to the register. x1x_xxxxb: reserved = 1 1xx_xxxxb: reserved = 1 a7 reserved =1b 6d a13:a8 30h soft reset and rescue sequence suppor t x1_xxxxb: reset enable instruction 66h is issued followed by reset instruction 99h. 1x_xxxxb: exit 0-4-4 mode is require d prior to other reset sequences. a15:a14 exit 4-byte addressing not supported 6e a23:a16 c0h exit 4-byte addressing not supported a21:a14 = 000000b a23 and a22 are reserved bits which are = 1 6f a31:a24 80h enter 4-byte addressing not supported 1xxx_xxxx: reserved = 1 jedec sector map parameter table 100h a7:a0 ffh sector map a7:a2=reserved=111111b a1=descriptor type = map=1b a0=last map = 1b 101h a15:a8 00h configuration id = 00h 102h a23:a16 04h region count = 5 regions 103h a31:a24 ffh reserved = ffh 104h a7:a0 f3h region 0 supports 4 kbyte erase and 8 kbyte erase a3:a0=0011b a7:a4=reserved=1111b table 11-1: serial flash discoverable parameter (sfdp) (continued) (9 of 16) address bit address data comments
? 2014-2015 microchip technology inc. ds20005262c-page 67 sst26vf016b 105h a15:a8 7fh region 0 size 4 * 8 kbytes = 32 kbytes count=32 kbytes/256 bytes= 128 value = count -1 =127 a31:a8 = 00007fh 106h a23:a16 00h 107h a31:a24 00h 108h a7:a0 f5h region 1 supports 4 kbyte erase and 32 kbyte erase a3:a0 = 0101b a7:a4=reserved = 1111b 109h a15:a8 7fh region 1 size 1 * 32kbytes = 32kbytes count=32kbytes/256 bytes= 128 value = count -1 =127 a31:a8 = 00007fh 10ah a23:a16 00h 10bh a31:a24 00h 10ch a7:a0 f9h region 2 supports 4 kbyte erase and 64 kbyte erase a3:a0 = 1001b a7:a4=reserved = 1111b 10dh a15:a8 ffh region 2 size 30 * 64 kbytes = 1920 kbytes count=1920 kbytes/256 bytes= 7680 value = count -1 =7679 a31:a8 = 001dffh 10eh a23:a16 1dh 10fh a31:a24 00h 110h a7:a0 f5h r egion 3 supports 4 kbyte erase and 32 kbyte erase a3:a0 = 0101b a7:a4=reserved = 1111b 111h a15:a8 7fh region 3 size 1 * 32 kbytes = 32 kbytes count=32 kbytes/256 bytes= 128 value = count -1 =127 a31:a8 = 00007fh 112h a23:a16 00h 113h a31:a24 00h 114h a7:a0 f3h region 4 supports 4 kbyte erase and 8 kbyte erase a3:a0=0011b a7:a4=reserved=1111b 115h a15:a8 7fh region 4 size 4 * 8 kbytes = 32 kbytes count=32 kbytes/256 bytes= 128 value = count -1 =127 a31:a8 = 00007fh 116h a23:a16 00h 117h a31:a24 00h table 11-1: serial flash discoverable parameter (sfdp) (continued) (10 of 16) address bit address data comments
sst26vf016b ds20005262c-page 68 ? 2014-2015 microchip technology inc. sst26vf016b (vendor) parameter table sst26vf016b identification 200h a7:a0 bfh manufacturer id 201h a15:a8 26h memory type 202h a23:a16 41h device id sst26vf016b=41h 203h a31:a24 ffh reserved. bits default to all 1?s. sst26vf016b interface 204h a2:a0 b9h interfaces supported 000: spi only 001: power up default is spi; quad can be enabled/disabled 010: reserved : : 111: reserved a3 supports enable quad 0: not supported 1: supported a6:a4 supports hold#/reset# function 000: hold# 001: reset# 010: hold/reset# 011: hold# & i/o when in sqi( 4-4-4), 1-4-4 or 1-1-4 read a7 supports software reset 0: not supported 1: supported 205h a8 dfh supports quad reset 0: not supported 1: supported a10:a9 reserved . bits default to all 1?s a13:a11 byte-program or page-program (256 bytes) 011: byte program/page program in spi and quad page program once quad is enabled a14 program-erase suspend supported 0: n ot supported 1: program/erase suspend supported a15 deep power-down mode supported 0: not supported 1: deep power-down mode supported table 11-1: serial flash discoverable parameter (sfdp) (continued) (11 of 16) address bit address data comments
? 2014-2015 microchip technology inc. ds20005262c-page 69 sst26vf016b 206h a16 fdh otp capable (security id) supported 0: not supported 1: supported a17 supports block group protect 0: not supported 1: supported a18 supports independent block protect 0: not supported 1: supported a19 supports independent non volatile lock (block or sector becomes otp) 0: not supported 1: supported a23:a20 reserved. bits default to all 1?s. 207h a31:a24 ffh reserved. bits default to all 1?s. 208h a7:a0 30h v dd minimum supply voltage 2.3v (f230h) 209h a15:a8 f2h 20ah a23:a16 60h v dd maximum supply voltage 3.6v (f360h) 20bh a31:a24 f3h 20ch a7:a0 32h typical time out for byte-program: 50 s typical time out for byte program is in s. represented by conversion of the actual time from the decimal to hexadecimal number. 20dh a15:a8 ffh reserved. bits default to all 1?s. 20eh a23:a16 0ah typ time out for page program : 1.0ms (xxh*(0.1ms) 20fh a31:a24 12h typical time out for se ctor-erase/block-erase: 18 ms typical time out for sector/block-erase is in ms. represented by conversion of the actual time from the decimal to hexadecimal number. 210h a7:a0 23h typical time out for chip-erase: 35 ms typical time out for chip-erase is in ms. represented by conversion of the actual time from the decimal to hexadecimal number. 211h a15:a8 46h max. time out for byte-program: 70 s typical time out for byte program is in s. represented by conversion of the actual time from the decimal to hexadecimal number. 212h a23:a16 ffh reserved. bits default to all 1?s. 213h a31:a24 0fh max time out for page-program: 1.5ms. typical time out for page program in xxh * (0.1ms) ms 214h a7:a0 19h max. time out for sector erase/block erase: 25ms. max time out for sector/block erase in ms 215h a15:a8 32h max. time out for chip erase : 50ms. max time out for chip erase in ms. 216h a23:a16 0fh max. time out for program security id: 1.5 ms max time out for program secu rity id in xxh*(0.1ms) ms 217h a31:a24 19h max. time out for write-protection enable latency: 25 ms max time out for write-protection enable latency is in ms. represented by con- version of the actual time from the decimal to hexadecimal number. 218h a23:a16 19h max. time write-suspend latency: 25 s max time out for write-suspend latency is in s. represented by conversion of the actual time from the decimal to hexadecimal number. 219h a31:a24 03h max. time to deep power-down: 3s = 03h) table 11-1: serial flash discoverable parameter (sfdp) (continued) (12 of 16) address bit address data comments
sst26vf016b ds20005262c-page 70 ? 2014-2015 microchip technology inc. 21ah a23:a16 0ah max. time out from deep power-down mode to standby mode: 10 s = 0ah 21bh a31:a24 ffh reserved. bits default to all 1?s. 21ch a23:a16 ffh reserved. bits default to all 1?s. 21dh a31:a24 ffh reserved. bits default to all 1?s. 21eh a23:a16 ffh reserved. bits default to all 1?s. 21fh a31:a24 ffh reserved. bits default to all 1?s. supported instructions 220h a7:a0 00h no operation 221h a15:a8 66h reset enable 222h a23:a16 99h reset memory 223h a31:a24 38h enable quad i/o 224h a7:a0 ffh reset quad i/o 225h a15:a8 05h read status register 226h a23:a16 01h write status register 227h a31:a24 35h read configuration register 228h a7:a0 06h write enable 229h a15:a8 04h write disable 22ah a23:a16 02h byte program or page program 22bh a31:a24 32h spi quad page program 22ch a7:a0 b0h suspends program/erase 22dh a15:a8 30h resumes program/erase 22eh a23:a16 72h read block-protection register 22fh a31:a24 42h write block protection register 230h a7:a0 8dh lock down block protection register 231h a15:a8 e8h non-volatile write-lock down register 232h a23:a16 98h global block protection unlock 233h a31:a24 88h read security id 234h a7:a0 a5h program user security id area 235h a15:a8 85h lockout security id programming 236h a23:a16 c0h set burst length 237h a31:a24 9fh jedec-id 238h a7:a0 afh quad j-id 239h a15:a8 5ah sfdp 23ah a23:a16 b9h deep power-down mode 23bh a31:a24 abh release deep power-down mode 23ch a4:a0 06h (1-4-4) spi nb burst with wrap number of wait states (dummy clocks) needed before valid output 00110b : 6 clocks of dummy cycle a7:a5 (1-4-4) spi nb burst with wrap number of mode bits 000b: set mode bits are not supported 23dh a15:a8 ech (1-4-4) spi nb burs t with wrap opcode table 11-1: serial flash discoverable parameter (sfdp) (continued) (13 of 16) address bit address data comments
? 2014-2015 microchip technology inc. ds20005262c-page 71 sst26vf016b 23eh a20:a16 06h (4-4-4) sqi nb burst with wrap number of wait states (dummy clocks) needed before valid output 00110b: 6 clocks of dummy cycle a23:a21 (4-4-4) sqi nb burst with wrap number of mode bits 000b: set mode bits are not supported 23fh a31:a24 0ch (4-4-4) sqi nb burs t with wrap opcode 240h a4:a0 00h (1-1-1) read memory number of wait states (dummy clocks) needed before valid output 00000b: wait states/dummy clocks are not supported. a7:a5 (1-1-1) read memory number of mode bits 000b: mode bits are not supported, 241h a15:a8 03h (1-1-1) read memory opcode 242h a20:a16 08h (1-1-1) read memory at higher speed number of wait states (dummy clocks) needed before valid output 01000: 8 clocks (8 bits) of dummy cycle a23:a21 (1-1-1) read memory at higher speed number of mode bits 000b: mode bits are not supported, 243h a31:a24 0bh (1-1-1) read memory at higher speed opcode 244h a7:a0 ffh reserved. bits default to all 1?s. 245h a15:a8 ffh reserved. bits default to all 1?s. 246h a23:a16 ffh reserved. bits default to all 1?s. 247h a31:a24 ffh reserved. bits default to all 1?s. security id 248h a7:a0 ffh security id size in bytes example: if the size is 2 kbytes, this field would be 07ffh 249h a15:a8 07h 24ah a23:a16 ffh reserved. bits default to all 1?s. 24bh a31:a24 ffh reserved. bits default to all 1?s. memory organization/block protection bit mapping 1 24ch a7:a0 02h section 1: sector type number: sector type in jedec parameter table (bottom, 8 kbyte) 24dh a15:a8 02h section 1 number of sectors four of 8kb block (2 n ) 24eh a23:a16 ffh section 1 block protection bit start ((2 m ) +1)+ c, c=ffh or -1, m= 5 for 16mb address bits are read lock bit locations and even address bits are write lock bit locations. the most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. if the sign bit is zero, then the number is greater than or equal to zero, or positive. if the sign bit is one then the number is less than zero or negative. table 11-1: serial flash discoverable parameter (sfdp) (continued) (14 of 16) address bit address data comments security id range unique id (pre-programmed at factory) 0000h - 0007h user programmable 0008h - 07ffh
sst26vf016b ds20005262c-page 72 ? 2014-2015 microchip technology inc. 24fh a31:a24 06h section 1 (bottom) block protection bit end ((2 m ) +1)+ c, c=06h or 6, m= 5 for 16mb address bits are read lock bit locations and even address bits are write lock bit locations. the most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. if the sign bit is zero, then the number is greater than or equal to zero, or positive. if the sign bit is one then the number is less than zero or negative. 250h a7:a0 03h section 2: sector type number sector type in jedec parameter table (32kb block) 251h a15:a8 00h section 2 number of sectors one of 32kb block (2 n , n=0) 252h a23:a16 fdh section 2 block protection bit start ((2 m ) +1)+ c, c=fdh or -3, m= 5 for 16mb the most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. if the sign bit is zero, then the number is greater than or equal to zero, or positi ve. if the sign bit is one then the number is less than zero or negative. 253h a31:a24 fdh section 2 block protection bit end ((2 m ) +1)+ c, c=fdh or -3, m= 5 for 16mb the most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. if the sign bit is zero, then the number is greater than or equal to zero, or positi ve. if the sign bit is one then the number is less than zero or negative. 254h a7:a0 04h section 3: sector type number sector type in jedec parameter table (64kb block) 255h a15:a8 05h section 3 number of sectors 126 of 64kb block (2 n -2, n= 5 for 16mb 256h a23:a16 00h section 3 block protection bit start section 3 block protection bit starts at 00h 257h a31:a24 fch section 3 block protection bit end ((2 m ) +1)+ c, c=fch or -4, m= 5 for 16mb 258h a7:a0 03h section 4: sector type number sector type in jedec parameter table (32kb block) 259h a15:a8 00h section 4 number of sectors one of 32kb block (2 n , n=0) 25ah a23:a16 feh section 4 block protection bit start ((2 m ) +1)+ c, c=feh or -2, m= 5 for 16mb the most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. if the sign bit is zero, then the number is greater than or equal to zero, or positi ve. if the sign bit is one then the number is less than zero or negative. 25bh a31:a24 feh section 4 block protection bit end ((2 m ) +1)+ c, c=feh or -2, m= 5 for 16mb the most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. if the sign bit is zero, then the number is greater than or equal to zero, or positi ve. if the sign bit is one then the number is less than zero or negative. 25ch a7:a0 02h section 5 sector type number: sector type in jedec parameter table (top, 8 kbyte) 25dh a15:a8 02h section 5 number of sectors four of 8kb block (2^n) table 11-1: serial flash discoverable parameter (sfdp) (continued) (15 of 16) address bit address data comments
? 2014-2015 microchip technology inc. ds20005262c-page 73 sst26vf016b 11.1 mapping guidance details the sfdp memory organization/block protection bit mapping defines the memory organization including uniform sector/block sizes and different contiguous sectors/blocks sizes. in addition, this bit defines the number of these uniform a nd different sectors/blocks from address 000000h to the full range of memory and the associated block locking r egister bits of each sec- tor/block. each major section is defined as follows: a major section consists of sector type number, num- ber of sector of this type, and the block-protection bit start/end locations. this is ti ed directly to jedec flash parameter table sector size type (in 7th dword and 8th dword section). note that the contiguous 4kbyte sectors across the full memory range are not included on this section because they are not defined in the jedec flash parameter table sector size type sec- tion. only the sectors/bl ocks that are dependently tied with the block-protection regi ster bits are defined. a major section is a partition of contiguous same-size sectors/blocks. there will be several major sections as you dissect across memory from 000000h to the full range. similar sector/block size that re-appear may be defined as a different major section. 11.1.1 sector type number sector type number is t he sector/block size typed defined in jedec flash parameter table: sfdp address locations 4ch, 4eh, 50h and 52h. sector type 1, which is represented by 01h, is located at address 4ch. sector type 2, which is represented by 02h, is located at address location 4eh. sector type 3, which is represented by 03h, is located at address location 50h. sector type 4, represented by 04h, is located at address location 52h. contiguous same sector type # size can re-emerge across the memory range and this sector type # will indicate that it is a separate/independent major section from the previous contiguous sectors/blocks. 11.1.2 number of sectors number of sectors represen ts the number of contigu- ous sectors/blocks with sim ilar size. a formula calcu- lates the contiguous sector s/blocks with similar size. given the sector/block size, type, and the number of sectors, the address range of these sectors/blocks can be determined along with specific block locking reg- ister bits that control the read/write protection of each sectors/blocks. 11.1.3 block-protection register bit start location (bpsl) block-protection register bit start location (bpsl) designates the start bit location in the block-protection register where the first sect or/block of this major sec- tion begins. if the value of bpsl is 00h, this location is 25eh a23:a16 07h section 5 block protection bit start ((2 m ) +1)+ c, c=07h or 7, m= 5 for 16mb address bits are read lock bit locations and even address bits are write lock bit locations. the most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. if the sign bit is zero, then the number is greater than or equal to zero, or positive. if the sign bit is one then the number is less than zero or negative. 25fh a31:a24 0eh section 5 (bottom) block protection bit end (((2 m ) +1)+ c, c=0eh or 14, m= 5 for 16mb address bits are read lock bit locations and even address bits are write lock bit locations. the most significant (left-most) bit indicates the sign of the integer; it is sometimes called the sign bit. if the sign bit is zero, then the number is greater than or equal to zero, or positive. if the sign bit is one then the number is less than zero or negative. 1. see ?mapping guidance details? for more detailed mapping information table 11-1: serial flash discoverable parameter (sfdp) (continued) (16 of 16) address bit address data comments table 11-2: section definition major section x section x: sector type number section x: number of sectors section x: block-protection register bit start location section x: block-protection register bit end location
sst26vf016b ds20005262c-page 74 ? 2014-2015 microchip technology inc. the 0 bit location. if the value is other than 0, then this value is a constant value adder (c) for a given formula, (2 m + 1) + (c) . see ?memory configuration?. from the initial location, there will be a bit location for every increment by 1 until it reaches the block protec- tion register bit end locat ion (bpel). this number range from bpsl to bpel will correspond to, and be equal to, the number of sect ors/blocks on this major section. 11.1.4 block protection register bit end location (bpel) block protection register bit end location designates the end bit location in the block protection register bit where the last sector/block of this major section ends. the value in this field is a constant value adder (c) for a given formula or equation, (2 m + 1) + (c) . see ?mem- ory configuration? 11.1.5 memory configuration for the sst26vf016b family, the memory configura- tion is setup with different contiguous block sizes from bottom to the top of the memory. for example, starting from bottom of memory it has four 8kbyte blocks, one 32kbyte block, x number of 64kbyte blocks depending on memory size, then one 32kbyte block, and four 8kbyte block on the top of memory. see ta b l e 11 - 3 . classifying these sector/blo ck sizes via the sector type derived from jedec flash parameter table: sfdp address locations 4eh, 50h, and 52his as fol- lows: ? 8 kbyte blocks are classified as sector type 2 (@4eh of sfdp) ? 32 kbyte blocks are classified as sector type 3 (@50h of sfdp) ? 64 kbyte blocks are classified as sector type 4 (@52h of sfdp) for the number of sectors associated with the contig- uous sectors/blocks, a formul a is used to determine the number of sectors/blocks of these sector types: ? 8kbyte block (type 2) is calculated by 2 n . n is a byte. ? 32kbyte block (type 3) is calculated by 2 n . n is a byte. ? 64kbyte block (type 4) is calculated by (2m - 2). m can either be a 4, 5, 6, 7 or 8 depending on the memory size. this m field is going to be used for the 64kbyte block section and will also be used for the block protection register bit location for- mula. m will have a constant value for specific densities and is defined as: table 11-3: memory bloc k diagram representation 8 kbyte bottom block (from 000000h) section 1: sector type number section 1: number of sectors section 1: block-protection register bit start location section 1: block-protection register bit end location 32 kbyte section 2: sector type number section 2: number of sectors section 2: block-protection register bit start location section 2: block-protection register bit end location 64 kbyte section 3: sector type number section 3: number of sectors section 3: block-protection register bit start location section 3: block-protection register bit end location 32 kbyte section 4: sector type number section 4: number of sectors section 4: block-protection register bit start location section 4: block-protection register bit end location 8 kbyte (top block) section 5: sector type number section 5: number of sectors section 5: block-protection register bit start location section 5: block-protection register bit end location
? 2014-2015 microchip technology inc. ds20005262c-page 75 sst26vf016b ?8mbit = 4 ? 16mbit = 5 ? 32mbit = 6 ? 64mbit = 7 ? 128mbit = 8 block protect register start/end bits are mapped in the sfdp by using the formula (2 m + 1) + (c) . ?m? is a con- stant value that represents the different densities from 8mbit to 128mbit (used also in the formula calculating number of 64kbyte blocks above). the values that are going to be placed in the block protection bit start/end field table are the constant value adder (c) in the for- mula and are represented in two?s compliment except when the value is 00h. if the value is 00h, this location is the 0 bit location. if the value is other than 0, then this is a constant value adder (c) that will be used in the for- mula. the most significant (left most) bit indicates the sign of the integer; it is sometimes called the sign bit. if the sign bit is zero, then the number is greater than or equal to zero, or positive. if the sign bit is one, then the number is less than zero, or negative. see ta b l e 11 - 4 for an example of this formula. table 11-4: bpsl/bpel equation with act ual constant adder derived from the formula (2 m + 1) + (c) block size 8 mbit to 128 mbit comments 8 kbyte (type 2) bottom bpsl = (2 m + 1) + 0ffh bpel = (2 m + 1) + 04h 0ffh = -1; 06h = 6 odd address bits are read-lock bit locations and even address bits are write-lock bit locations. 32 kbyte (type3) bpsl = bpel= (2 m + 1) + 0fdh 0fdh= -3 64 kbyte (type 4) bpsl = 00h bpel = (2 m + 1) + 0fch 00h is block-protection register bit 0 location; 0fch = -4 32 kbyte (type 3) bpsl = bpel= (2 m + 1) + 0feh 0feh=-2 8 kbyte (type 2) top bpsl = (2 m + 1) + 07h bpel = (2 m + 1) + 0eh 07h = 7; 0eh = 14 odd address bits are read-lock bit locations and even address bits are write-lock bit locations.
ds20005262c-page 76 advance information ? 2014-2015 microchip technology inc. information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, th e microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip te chnology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microc hip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered tradem ark of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2014-2015, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-63277-661-7 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem by dnv == iso/ts 16949 ==
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